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```
./configure --enable-sky130-pdk=/host/skywater-pdk --enable-alpha-sky130 --prefix=/usr/local --enable-klayout --disable-magic --disable-netgen --disable-irsim --disa
ble-openlane --disable-qflow…
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PDK was installed using volare from earlier in the README.md
```
make verify-mprj_por
docker run -v /home/foo/efabless/caravel_user_project_analog:/home/foo/efabless/caravel_user_project_analog -…
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## Expected Behavior
For each Technology LEF for each STD library, there should exist a specification for the minimum enclosed area rule: "Min area of metal2 holes > 0.14um^2" and "Min area of meta…
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Seen on `slot-012` of chipignite `2206q_b`.
- Lower levels do not have text or pins.
- nwell is extracted as connected to `#m4_x_y` (autogenerated name) at level 3 (not a port).
- Level 2 has no…
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## Expected Behavior
Line 16 should read
`* include "sky130_fd_pr__esd_nfet_05v0_nvt.pm3"`
## Actual Behavior
Line 16 now is:
`include "sky130_fd_pr__esd_nfet_05v0_nvt.pm3"`
Because of leadi…
holvo updated
5 months ago
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## Expected Behavior
The `endif` directive should be followed by the macro name commented out. Correct behavior is like
`endif // SKY130_FD_SC_HD__LPFLOW_BLEEDER_FUNCTIONAL_PP_V`
where the m…
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## Expected Behavior
Verilog views shouldn't have any syntax errors.
## Actual Behavior
The behavioral model for the `sky130_fd_sc_hd__dlxbn` has an invalid verilog syntax at `wire 1;`
T…
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Currently open_pdks installs technology file in the current directory layout:
```
/home/proppy/.volare/sky130A/libs.tech/klayout
/home/proppy/.volare/sky130A/libs.tech/klayout/drc
/home/proppy/.vo…
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I haven't had a chance to look at this closely yet, so this is somewhat of a guess, the continous builder has been failing for ~8 days due to the following;
```
+ find /host/out/pdk-all /host/out/pd…
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After an open_pdks update most pm3 fet model files no longer have the gauss() functions for simulating montecarlo/mismatch. For example, expression for vth0 for a nfet_01v8 transistor (`.../share/pdk/…