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Especially for cryptography tasks hardware ISA should provide some basic security approaches to prevent physical, lifecycle and software attacks. What do you think are the security measures other than…
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It can increase Wine runner performance, because runner can use more CPU instructions.
[x86-64-v3 benchmarks](https://lists.archlinux.org/pipermail/arch-general/2021-March/048739.html)
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[MeltdownPrime.pdf](https://github.com/kermitt2/grobid/files/1899022/MeltdownPrime.pdf)
Specifically References 13, 14 and 15 in the attached document. Yatin A. Manerkar is parsed as A Yatin, then i…
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The `archspec.cpu.host` function was changed in archspec 0.1.3 (see https://github.com/archspec/archspec/pull/53) to return the best matching generic CPU microarchitecture level if there's no exact ma…
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I'm interested in doing some custom benchmarks on OpenPiton + Ariane.
Is there a way to get the l1.5 and l2 miss rate from the simulations? Running
``` sims -sys=manycore -x_tiles=1 -y_tiles=1…
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This snippet of code in your `set_context` subroutine:
```asm
pushq %r8
xorl %eax, %eax
ret
```
should be changed to:
```asm
xorl %eax, %eax
jmp *%r8
```
And likewise with…
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Processor Counter Monitor (2022-03-07 16:06:44 +0100 ID=fd11f3f)
===== Processor information =====
Linux arch_perfmon flag : yes
Hybrid processor : no
IBRS and IBPB supported :…
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Right now you can only specify a single alignment offset manually. It would be useful to offer an option where uiCA performs its simulation for all possible alignment offsets and gives you error bars …
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They recently defined microarchitecture levels for x86-64 ([Wikipedia](https://en.wikipedia.org/wiki/X86-64#Microarchitecture_levels)) but apparently decided against including AES in any of them. So i…
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**Type of issue**: feature request
**Impact**: no functional change
**Development Phase**: request
**Other information**