chipsalliance rocket-chip issues

chipsalliance / rocket-chip

Rocket Chip Generator

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issues

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unable to build the C emulator due to missing verilog.h file

#3656 nhuynh368 opened 5 days ago
0
Move rocket-related config fragments to rocket/Configs.scala

#3655 jerryz123 opened 1 week ago
0
Adding new config fragments to Rocket-chip subsystem Config.scala

#3654 Kevin99214 closed 1 week ago
2
Replay queue depth insufficient for RoCC accelerators

#3653 PhilippKaesgen opened 1 week ago
0
Allow non-V implementations of vector units, with Zve/Zvl extensions

#3652 jerryz123 closed 1 week ago
0
PTW: traverse check GPA bits higher than HGATP mode only if leaf

#3651 ingallsj closed 1 week ago
0
Migrate rocketchip utils to standalone library

#3650 lordspacehog opened 2 weeks ago
8
vcs compile error

#3649 dimory opened 2 weeks ago
0
Interrupts coming outwards from the Tile should cross into a toPlicDomain

#3648 jerryz123 closed 3 weeks ago
0
Bus Error Unit cannot find implicit clock when RocketTile crossingType is set to RationalCrossing

#3647 Kevin99214 closed 3 weeks ago
2
class RocketChip$macro$3 needs to be abstract.

#3646 Amagicman closed 3 weeks ago
2
Add "MergedCreditedCrossing" for TileLink channels

#3645 jerryz123 opened 3 weeks ago
1
Error: Assertion failed: 'A' channel re-used a source ID when running simulation in QuestaSim

#3644 DonnieThang opened 1 month ago
1
the usage of cover and cover point, and how to coordinate with backend.

#3643 zhao-denghui opened 1 month ago
1
Move clocking/resources out of diplomacy subpackage

#3642 jerryz123 closed 3 weeks ago
0
Set parameterized desiredName on many system components

#3641 jerryz123 closed 1 week ago
0
Name the ClockDomains

#3639 jerryz123 closed 1 month ago
2
Add support for desiredName overrides for ClockDomains

#3638 bchetwynd closed 1 month ago
1
Add IO Connections for Custom User Field in TL Channels within Xbar

#3637 ksungkeun84 opened 1 month ago
6
Debugging section of README.md leads nowhere

#3636 Nerotos opened 1 month ago
0
RoCC: io.mem.req.ready stuck

#3635 ARF1939261764 opened 1 month ago
0
Update APBtoTL scala to not flip apb address when doing conversion

#3634 Kevin99214 closed 1 month ago
1
MCAUSE register holds wrong exception

#3633 bantierr opened 1 month ago
1
HART specific opearations at DRAM controller / adding hartid to memory requests

#3632 FelixWagner00 opened 1 month ago
0
Minor FPU imropvements

#3631 jerryz123 closed 1 month ago
0
Discrepency between simulation with and without traces

#3630 bantierr closed 1 month ago
2
Rocket updates sepc and stval in M mode

#3629 zhangkanqi closed 1 month ago
2
Suggest name for plic domain

#3628 joonho3020 closed 1 month ago
0
Fix extraction-width warnings

#3626 jerryz123 closed 2 months ago
0
PTW: traverse check GPA bits higher than HGATP mode only if valid

#3625 ingallsj closed 2 months ago
0
Hypervisor: drive mtinst/htinst

#3624 ingallsj closed 2 months ago
0
Error when building the project

#3623 iagrigorov opened 2 months ago
2
Update ICache.scala

#3621 srishti-sr closed 2 months ago
1
[Proposal] Nextgen rocket-chip planning thread.

#3620 lordspacehog opened 2 months ago
9
Verilog generation

#3619 srishti-sr closed 2 months ago
1
Mill resolve error

#3618 srishti-sr closed 2 months ago
1
Unable to make verilog

#3617 ic-ssc closed 2 months ago
1
Use SV48 when possible

#3616 abejgonzalez closed 2 months ago
2
Update SRAM.scala to improve perf on non-full sized reads

#3614 Kevin99214 closed 2 months ago
0
Add illegal instruction detection to RVC decoder

#3613 chenguokai closed 2 months ago
8
Fix compile error for chisel 6.0.0

#3612 sashimi-yzh opened 2 months ago
2
Using make Config Generated Verilog with TestHarness in Vivado for Logic Synthesis

#3611 fengmu0124 closed 2 months ago
1
Unused standard parts of mie register not properly implementing read-only 0

#3610 tzwaenn opened 3 months ago
1
Remove Scalar Crypto and BitManip?

#3609 csgxiong closed 2 months ago
2
Fix tile interrupt sources

#3608 jerryz123 closed 3 months ago
1
Bus error unit cannot be added, fails diplomacy

#3607 Kevin99214 closed 3 months ago
2
Fix connection order of meip/seip to plic

#3606 jerryz123 closed 3 months ago
0
Fix chisel3.experimental imports in debug/Periphery

#3605 jerryz123 closed 3 months ago
1
[Proposal] Refactor the remaining helpers out of the diplomacy module in rocket-chip.

#3604 lordspacehog opened 3 months ago
5
parameter not find in freechips.rocketchip.config

#3603 tangjiaping opened 3 months ago
1