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While updating our tools to a later version of Verilator and updating the lint flags to Verilog-2005 we came across a few new warnings, see below.
We don't have a quick solution to this for a few …
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Coq sometimes misinterpret Verilog HW description language files as being Coq prover language files.
There has been a number of issues opened related to this. But all of them has been closed without …
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I'm looking for reset ports in `picorv32` design synthesized on `sky130hd`. There is one reset port called `resetn`. However, I get different results for the following two commands:
```
% get_ports …
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Bonjour,
A naive question, I am porting and benchmark the AES and PQC algorithm on picoRV32. Easiest way I could find to execute with verilator is to modify the hello.c and different files from there…
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I personally think `CriticalSection` should not be `Clone`, because of two use case requiring that:
- [`interrupt::enable_cs`](https://docs.rs/msp430/0.2.2/msp430/interrupt/fn.enable_cs.html): Safe…
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I am using rdcycle instruction to calculate number of clock cycles consumed for operation but I see some high number of clock cycles on PicoRV32 with Verilator. So I tried basic code of a++
```
…
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I added some code that required stdlib as I removed -nostdlib from Makefile present in root directory of this repository and I see that memory region has been increased that is causing failure even so…
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@nand2mario, so I've been checking [Design notes for SNESTang](https://github.com/nand2mario/snestang/blob/main/doc/design.md), [Adding a Softcore to SNESTang - part 1](https://nand2mario.github.io/po…
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Hello,
I've build the Ibex safe version for the Arty A7 100T board at 33MHz.
I've a correct result on /dev/ttyUSB1:
```
Ready to load firmware, hold BTN0 to ignore UART input.
```
I've build…
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Les PCPI ont été déterminés comme non nécessaire selon @psycotrop.
J'avais vu que dans le git du picorv32 il était possible d'avoir un coeur sans cette fonctionnalité.
Il faudrait essayer de faire…