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Hi Alex,
When I ran the test using python3 test_fpga_core.py, I met the issue as follows,
Running test...
../rtl/fpga_core.v:1075: sorry: constant user functions are not currently supported: w_…
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Idea is to
- Install all the required tools/libraries inside a common folder
- Have a project.csh and set the environment variable accordingly.
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**the cocotb version used:** cocotb-1.6.2
**the operating system and version (32/64 bit):** m1 mac
**the simulator and version (32/64 bit):** homebrew icarus-verilog 11.0
**the Python version, and …
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Verilog like parameters for module for debugging purposes.
**Type of issue**: feature request
**What is the use case for changing the behaviour?**
It would be great to have a possibility to ser…
Nic30 updated
5 years ago
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Here are some ideas for speeding up our testing:
* Use mlir-verilog by default rather than coreir-verilog. I believe this is already a goal of magma 3.0.
* Avoid compilation when possible. I.e. us…
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This is a task tracker for all issues related to floating point.
The following is a full list of all the bfloat16 operations we need to support organized by priority. In general if these can be gen…
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Icarus freezes when analyzing the program below:
```systemverilog
module module_0 #(
parameter id_1 = 32'd36
);
initial begin
if (id_1) begin
if (id_1[(id_1[1'b0-{id_1, id_1}…
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Hi Neemann!
In order to fill memory contents I code in Verilog file:
initial $readmemh("RV32I_memory.txt",Memory);
I can with success the file in Digital, and export also the design file to Verilog…
j054n updated
2 years ago
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Is it possible to add a delay to a component (such as an and gate) that gets exported to the verilog netlist?
In other words, instead of generating "assign x = (a & b)" generate "assign #1 x = (a &…
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Hi,
I replaced Questa Advanced Simulator with GHDL to get a VHDL programming environment with open source components.
Link to my fork: https://github.com/roy77/logisim-evolution
It works. Only inou…
roy77 updated
3 years ago