steveicarus iverilog issues

steveicarus / iverilog

Icarus Verilog

https://steveicarus.github.io/iverilog/

GNU General Public License v2.0

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issues

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VPI: reading time properties

#1172 r2com closed 1 week ago
5
Icarus freezes when analyzing program

#1171 joaovam opened 2 weeks ago
5
Tsizer returns an error with -g2012

#1170 dmitrystu opened 2 weeks ago
1
Warning of missing drive by constant 0

#1169 jiangshuirou closed 2 days ago
5
Fix vvp cg array word aliasing

#1168 martinwhitaker closed 3 weeks ago
0
inout ports driver collisions handled improperly

#1167 tarik-ibrahimovic closed 2 weeks ago
3
tgt-vvp: Use signedness of expression instead of signal for index load

#1166 larsclausen closed 3 weeks ago
0
Incorrect result from shift operation

#1165 Jiabao1125 closed 3 weeks ago
2
Fix vector assignment with undefined delay

#1164 larsclausen closed 3 weeks ago
0
The return type of $bits should be `integer`, not an unsigned type.

#1163 zachjs closed 3 weeks ago
2
tgt-vvp: Replace `%pushi ...; %op` with `%opi`

#1162 larsclausen closed 3 weeks ago
0
During simulation, hdl_out was incorrectly assigned a value.

#1161 zhu-jinbo closed 2 weeks ago
3
A question about discipline.vams in Candence

#1159 KingJin0915 closed 1 month ago
1
VPI: callback function scheduling itself

#1158 r2com closed 1 month ago
0
vvp hangs forever on msys2 but does not on linux

#1157 Kreijstal opened 1 month ago
25
During simulation, iverilog mistakenly assigned a value to an undriven variable.

#1156 llb-del closed 1 month ago
3
Compiler fails to initialize array value for vvp

#1155 ericastor closed 3 weeks ago
9
Trying to use IVerilog throws "The system cannot find the path specified" error on Windows

#1154 pedromvnreis closed 1 month ago
1
Save and Restore simulation state

#1153 AruneshKma opened 1 month ago
2
iverilog err cannot found CXX_ABI_1.3.8

#1152 userwzm closed 1 month ago
2
During simulation, iverilog incorrectly assigned a value to a variable that was not driven.

#1151 ghost closed 1 month ago
9
Simulation mismatches in RTL vs post synthesis netlist(Yosys generated) co_simulation

#1150 abdulhameed-akram closed 2 months ago
2
Unpacked localparam array support

#1149 lefp opened 2 months ago
0
Simulation results discrepancy

#1148 LoSyTe closed 2 weeks ago
3
Assertion Failure in AST Processing: node->bits == v at frontends/ast/ast.cc:855

#1147 1353369570 closed 2 months ago
1
infinant loop in recursive function causes crash

#1146 Adivinedude closed 2 months ago
2
icarus gets caught in a infinite combi loop and I'm not sure why.

#1145 sean-galloway closed 1 month ago
13
$display not working inside function during non clocked execution

#1144 Adivinedude closed 2 months ago
2
incomplete for statement produces no output.

#1143 Adivinedude closed 2 months ago
9
no warning for scaler being access with indexed part select. No warning for double assignment of combiniational logic

#1142 Adivinedude closed 2 months ago
2
function being classified as non-constant

#1141 Adivinedude closed 3 months ago
3
No error or warning reported when a vector lsb or msb value contains `x` or `z` bits

#1140 Adivinedude opened 3 months ago
9
Uninformative "syntax error" message when an undefined package name is used

#1139 Kreijstal opened 3 months ago
4
Non-interactive mode of vvp (-n, -N) seems to be broken

#1138 msinger closed 3 months ago
3
Downgrade non-existing parameter to a warning (again)

#1137 olofk opened 3 months ago
1
Revive Action test.yml.

#1136 gatk555 closed 3 months ago
1
Changing Fixed VVP Path for Prebuilt Icarus Verilog on a Restricted System

#1135 Nado15 closed 3 months ago
3
Bug: assert: elab_expr.cc:2673: failed assertion base_index.size()+1 == net->packed_dimensions()

#1134 fzhwenzhou opened 4 months ago
3
Adding signal output will cause abnormal simulation output in iverilog

#1133 WeneneW closed 4 months ago
3
The simulation of iverilog and other tools is inconsistent

#1132 WeneneW closed 3 months ago
1
This code stalls instead of erroring

#1131 parker-research opened 4 months ago
2
Executing multiple `vvp` instances of different files in parallel on the same computer causes vvp to hang

#1130 parker-research closed 4 months ago
3
Please tag an official `v13.0.1`, or `v13.0.1-rc1`, or something

#1129 parker-research opened 4 months ago
6
Request: add `exit` alias to `vvp`'s terminal interface

#1128 parker-research opened 4 months ago
2
Possible infinite loop in output evaluation

#1127 NickOveracker opened 4 months ago
2
data_out in rtl outputs at same clock cycle as data_out_reg (Flip-Flop issue)

#1126 abdulhameed-akram closed 4 months ago
3
Clock of register is out of sync between RTL vs Yosys genereted netlist

#1125 zhergarvi closed 4 months ago
2
Arrays can't be used in sensitivity lists

#1123 mzannoni closed 4 months ago
6
Delayed transmission from tranif0/tranif1 primitives

#1122 NickOveracker closed 4 months ago
3
ivl: logic_lpm.c:485: find_local_signal: Assertion `! sig' failed.

#1120 vicencb opened 5 months ago
4