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> Note: I've tried on both `Windows10` and `Ubuntu 20.04.1 LTS`. The errors described below are the same on both systems.
I'm trying to connect `riscv-none-embed-gdb` - which is part of the xPack R…
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Hi @felipe-iar
I am planning to start working on a C++ project using the EWRISCV and the eval board.
Would be possible to clarify the prerequisites in order to create a C++ project under this sc…
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https://github.com/riscv-rust/gd32vf103-pac/blob/d98f791d2d4a39253b7b55182c147d56252563c0/src/timer1.rs#L281
I could be wrong about this, but it looks like timer 1 has the wrong size for the captur…
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When I tried to build as instructed with the stable toolchain, I got this:
```
$ cargo build --example blinky --release --all-features
Updating crates.io index
Downloaded riscv-target v0.1.2…
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_This is a Bug//Question/IDK TBH_
* **I have**
- [x] Searched previous issues
- [x] ~~This is in _this_ firmware, not vendor "offical" firmware~~ this is the vendor firmware
- [x] This is…
depau updated
3 years ago
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Hi Martin,
I came across this and though you might want to have a look at [gd32vf103inator](https://github.com/esmil/gd32vf103inator). The interrupt controller on the gd32vf103 has a [vectored mode…
esmil updated
4 years ago
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Eg. the STM32F446xx family has OTG_FS and OTG_HS cores which can function both as peripheral and host (for USB OTG). I would like to be able to use this crate with the OTG_FS core in peripheral mode. …
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- [x] **PlatformIO Core**.
If you’ve found a bug, please provide an information below.
*You can erase any parts of this template not applicable to your Issue.*
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Hi @felipe-iar
I need help!
I tried to use this template project available in the contributions folder as initial reference for my own project for the RISC-V eval board.
I followed all the ins…
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I tried to run QEMU (RISC-V) with the latest Eclipse CDT and the MCU plug-ins. What I did is to set up a debug configuration under GDB QEMU Debugging. But after setting, I run debug but got an error p…