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We need to upgrade the Xilinx compilation flow to target Vitis, which is the rebranded/repackaged version of SDx/SDAccel. This requires:
- [x] Updating hlslib to the newest version, which supports Vi…
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SDAccel_Examples/getting_started/rtl_kernel/rtl_streaming_free_running
Example Design giving errors when I tried to build
make all TARGET=hw_emu DEVICE=xilinx_u200_qdma_201910_1 check
logs:
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Running `make SOFTWARE=1` returns:
```
mkdir -p ./xclbin
/bin/xcpp -I./libs/xcl2 -I/include/ -Wall -O0 -g -std=c++14 -fmessage-length=0 main.cpp local_support.cpp support.cpp bench.cpp ./libs/xcl…
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I am trying to run the basic RTL vadd example(https://github.com/Xilinx/SDAccel_Examples/tree/master/getting_started/rtl_kernel/rtl_vadd) using the SDx 2019. I created a kernel using the RTL kernel Wi…
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We're trying to port Rosetta to the newest AWS AMI machines using SDAccel. Does the host code perform any sort of checking to make sure that the output generated by the accelerator is correct? For exa…
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According to [Vivado HLS documentation](https://gist.github.com/rachitnigam/188cb4edbf734e6785b3e90eb7c5da0a#interfaces), `s_axilite` interfaces should be generated for non-array arguments.
The wor…
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SDAccel generates a bunch of RPT files. We need to figure out which one are the right ones to extract data from.
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there is a fatal error: CL/cl_ext_xilinx.h: No such file or directory when I make the Makefile by HLS version. There is an solution I found in Xilinx Community https://forums.xilinx.com/t5/SDAccel/CL-…
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```In file included from bsg_manycore_uart_responder.cpp:1:0:
bsg_manycore_uart_responder.cpp: In destructor ‘{anonymous}::__bsg_manycore_uart_responder_add_del::~__bsg_manycore_uart_responder_add_de…
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Could you provide an example for 2d image fft in SDAccel, given that it's a very common image processing operation?