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Hi I have a problem sending my bitstream file to the ALPHA250 card I configured ethernet connection between the host and a Zynq board as precised on koheron website but I don't know what is the next …
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Hi,
i wanted to use zlog as Framework logging, first thing i wanted is to cross-compile for zynq and then use then customize it for logging purpose.
Please provide any …
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I want to run RISC-V rocket-chip on Zynq FPGA Board (Zybo Z7), what are the constraints I have to add to the project?
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_From @mithro on July 14, 2014 12:8_
The Xilinx Zynq-7000 series devices are a combined ARM processor with a "series 7" FPGA. The [Digilent ZYBO](http://www.digilentinc.com/Products/Detail.cfm?NavPat…
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Can you please tell whether we can use python to program Zedboard using the Pynq framework? I want to implement Mask RCNN algorithm on Xilinx Zedboard. Looking forward to your reply
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I discovered an apparent timing hazard in the low level Ethernet driver that does not correctly handle the scatter-gather DMA (SGDMA) ring descriptor if 2 packets are sent within 5 usec of one another…
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I encountered an error and had trouble figuring out what went wrong because the script just failed with "make indicated an error":
```
Running ['./scripts/feeds', 'install', '-a'] in /asdf/rebuild
…
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I there advantage disadvantage of using this adapter vs following this xilinx wiki on cache coherency? https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842098/Zynq+UltraScale+MPSoC+Cache+Cohere…
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I looked at this project since I'm trying to optimize a RAM - to - reseved RAM transfer on a 7 series Zynq device.
It looks you did really a great work! It's explained very clearly and seem easy to u…
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Hi ,
I have designed a zynq + ad9361 board which runs openwifi well .Hareware feature is : ZYNQ XC7Z020CLG400 ,1GB DDR3 memory fo PS, 1G ETHER RJ45 for PS,1G ETHER RJ45 for PL, USB OTG(act as USB ho…