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**Issue**
This isn't hard to reproduce with any of the provided examples, say `ctr.py`. Running `python ctr.py simulate -c 10`, for example, produces a Python traceback rather than a friendly error m…
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After trying to replace some `nmigen.compat.genlib.Record` usages with `nmigen.hdl.rec.Record`, I'm getting this error when attempting to run the `test_analyzer` test case on my litescope port, as can…
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At the moment, Yosys is a hard dependency of nMigen if `back.verilog` is used. Because of the debug Verilog output provided even in FOSS design flows (where the synthesis ingests RTLIL, not Verilog), …
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After fixing some nasty errors related to mixed spaces and tabs, I run
```
python 3Particles/simulator_WP0817_3Particles.py
```
and see an empty windows
![Screenshot 2019-04-04 at 20 35 40](htt…
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This snippet illustrates the issue:
```py
from nmigen import *
from nmigen.back import pysim
class Bug(Elaboratable):
def __init__(self):
self.reg = Signal()
self.out = …
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**Issue by [programmerjake](https://github.com/programmerjake)**
_Saturday Mar 23, 2019 at 01:09 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/47_
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I'm using nmigen d69a4e2…
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If I follow the steps outlined with a new sysmoUSIM-SJS1 everything proceeds fine up until the step 'gp --acr-list-aram', which results in:
Could not read A00000015141434C00
If I then execute gp…
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Hi @herlesupreeth ,
I have order a 10-pack SIM cards. It's green in color. I have tried 2 cards. KIC/KID/KIK are good. However, there are problem when trying --acr-list and the CoIMS cannot get c…
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When I run `pip install hiq-circuit` in my python virtual environment it failed.
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Pysim is slow at simulation (this gets much better with PyPy) and at elaboration (this gets worse with PyPy). Needs investigation as to why exactly.