m-labs nmigen issues - Githubissues

m-labs / nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

https://nmigen.org

Other

645 stars 55 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

For loops in Nmigen

#350 ParasVekariya opened 1 year ago
0
No clk being generated

#349 mayank-kabra2001 opened 2 years ago
0
nmigen install error

#348 ZhangPeterGree closed 2 years ago
1
Does nmigen support I2C master ?

#347 jimmymagemtek closed 2 years ago
1
Want to know some details of the back

#346 ekikun opened 3 years ago
1
Improve readability of assignments and add contexts for clock domains

#345 ildus opened 3 years ago
0
Update UART Example so that acknowledging RX data sets RX ready low.

#344 newhouseb opened 3 years ago
0
Fix broken timing constraints

#343 slan closed 3 years ago
0
Please add details that this repository is obsolete/not longer maintained anymore for new comer

#342 bvernoux closed 3 years ago
3
Python simulator hangs or throws when trying to drive reset from testbench

#341 hansfbaier closed 3 years ago
1
negative values support in Switch-Case

#340 weshu closed 3 years ago
1
Add variable keyword argument support to nmigen.hdl.rec.Record

#339 DonaldKellett opened 3 years ago
0
Add option to specify spec_name

#338 DonaldKellett closed 3 years ago
0
Add option to specify solver in nmigen.test.utils

#337 DonaldKellett closed 3 years ago
0
Allow more flexibility in FHDLTestCase assertFormal

#336 DonaldKellett closed 3 years ago
0
Convert tests to regex versions

#335 grvvy closed 3 years ago
0
Add initial support for Symbiflow toolchain for Xilinx 7-series

#334 mglb opened 3 years ago
0
Signal decoder inference for Enums doesn't work for Layout members

#333 shawnanastasio opened 4 years ago
0
Can't generate verilog for blinky example: Only signals may be added as ports

#332 shawnanastasio closed 4 years ago
1
lambdasoc analysis & synthesis got error on intel platform.

#331 franz-git opened 4 years ago
0
Fixes FileNotFoundError that happens when running formal proofs

#330 colepoirier closed 2 years ago
0
Generating async negedge reset

#329 tariqafzal opened 4 years ago
0
Hierarchical Redundancy in emitted Verilog

#328 BracketMaster opened 4 years ago
1
Can I create an active-low (asynchronous) reset?

#327 hofstee closed 4 years ago
0
Fix `_yosys_version()`

#326 hofstee closed 4 years ago
1
Bus arbiter broken after synthesis

#325 strobo5 closed 4 years ago
1
use declarative setuptools config

#324 graingert closed 4 years ago
0
Installation fails if wheel not installed

#323 alanvgreen opened 4 years ago
3
Release timeline

#322 FFY00 closed 4 years ago
2
Internal Oscillator Usage ICE40

#321 jchidley closed 4 years ago
7
Unable to Build and flash my board.

#320 teezzan closed 4 years ago
9
Index a signal with a slice from another signal

#319 rnd2 closed 4 years ago
2
Initial Class: ValueError: call stack is not deep enough

#318 goktug97 closed 4 years ago
4
Using Python to Formal Verify Verilog and VHDL Files

#317 goktug97 closed 4 years ago
4
Case pattern syntax improvement

#316 porglezomp closed 4 years ago
2
FSM with transition to nonexistent state should not elaborate

#315 awygle closed 4 years ago
1
How to pass yosys_opts to LatticeICE40Platform?

#314 RobertBaruch closed 4 years ago
2
build.dsl: allow strings to be used as connector numbers

#313 anuejn closed 4 years ago
3
Assignment to a Record with zero-width fields generates invalid Verilog

#312 jfng closed 4 years ago
3
Support for non integer connector / ressource 'numbers'

#311 anuejn closed 4 years ago
2
hdl.ast.Value.word_select() works incorrectly on actual platform (ECP5 Versa)

#310 ghost opened 4 years ago
5
vendor.lattice_{ice40,ecp5}: Support .il (RTLIL) files in extra_files

#309 smunaut closed 4 years ago
1
Support Platforms that include an existing design and expose interface to that design as Resource

#308 smunaut opened 4 years ago
0
AssertionError domain.name not in self.domains

#307 nicolas-robin closed 4 years ago
4
vendor.lattice_ecp5: Support internal oscillator (OSCG)

#306 miek closed 4 years ago
2
AssertionError with strange Switch

#305 Ravenslofty closed 4 years ago
1
ResetSynchronizer clockdomain in submodule is not renamed properly with multiple submodule instances

#304 povauboin closed 4 years ago
3
Usability? Can we warn if a Statement is never assigned to a domain?

#303 RobertBaruch closed 4 years ago
2
nmigen generates invalid RTLIL with negative shifts

#302 Ravenslofty closed 4 years ago
1
vendor.xilinx_7series: Vivado TIMING-2 Warning

#301 peteut closed 4 years ago
4