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### Is there an existing core-v-mcu bug for this?
- [X] I have searched the existing bug issues
### Bug Description
To do simulation using verilator and gtkwave
we are trying to "build verilator m…
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Hi Folks,
I enabled VERILOG and VERILATOR option in Makefile, and the co-simulation looks fine.
I run a baremetal program which writes data to APB timer at RTL side. From the waveform of apb timer, …
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Unfortunately, this still seems to be an issue in the 3.4.1 release.
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Performing C SOURCE FILE Test Intl_IS_BUILT_IN failed with the following output:
Change Dir: /tmp/apbs-20220926-39…
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```
val factory = AhbLite3SlaveFactory(io.ahblite)
val factory1 = Apb3SlaveFactory(io.apb)
val streamUnbuffered = factory.createAndDriveFlow(Bits(1 bits), address = 0x010).toStream //error occour
…
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Решение с фильтрацией массива переменных по вхождению `ID.includes(v.ID)`, где `typeof ID == 'string'`, не слишком удачное, потому что обнаруживает совпадения с лишними переменными: например, в "125" …
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There is no mention of this in the [prerequisites](https://github.com/ansibleplaybookbundle/ansible-playbook-bundle/blob/master/docs/apb_cli.md#prerequisites) section.
PS: https://github.com/opensh…
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I have an interrupt controller written in Verilog and I am able to convert this model to C++ using Verilator. I want to attach it to a Renode machine, however, there is a problem.
The interrupt c…
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The export of image texture node assets works very well, it seems a positive development in brush export.
There are a couple of details that seem to need revision...
1 - when importing a previou…
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It's not possible to configure an environment without any master or with a passive master. This would be useful when verifying an APB master (e.g. a bridge).
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This reason for this message is that I am seeing a system lockup when trying to use mt7612u based adapters. Yes, device drivers can do that. I was seeing it in kernel 6.1 rc1 and am still seeing it in…