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It might be interesting to support running `arachne`, `nextpnr` and `vpr` with and without carry support.
It's something which is interesting now but might not be interesting in the future. I'm cur…
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I'm developing on a BlackIce board, basically an ICE40 FPGA.
My code is a very simple counter on 4 LEDS, almost identical with a Blackice Tutorial example,
but with a software reset facility, whic…
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It would be good if tags were on this repository for releases.
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Could we make the --warn-no-port the default when reading the constraint file ?
At the moment, when absent, it's considered a fatal error to define a port there, and not have in in the top level. I d…
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As project size increases arachne-pnr has an increasing tendency to connect IO block clocks to global clock networks via an intermediate buffer and high-skew local net chain. This, in turn, destroys …
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Given the latest toolchain (for exact tracking you can check out `github.com/dpiegdon/IceStormToolchain.git`) and the project in `github.com/dpiegdon/orbuculum.git` branch `icestick-support` in direct…
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I use icestorm tools to program FPGA iCE40HX4K-TQ144.
According to specification this chip should have 3520 LUT's and 20 BRAM's, but when I invoke arachne-pnr (`arachne-pnr -d 8k -P tq144:4k ....`)…
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According to http://www.clifford.at/icestorm/io_tile.html for a 1K chip:
> When an input pin pair is used as LVDS pair ... then the four bits IoCtrl IE_0/IE_1 and IoCtrl REN_0/REN_1 are all set, as w…
mo101 updated
6 years ago
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I'm trying to get the following Verilog to compile, using SB_LVDS_INPUT. I can't find any examples online aside from the Lattice PDF, which I tried to follow, but am getting a failed assertion in arac…
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## Steps to reproduce the issue
When creating code in migen for use with Vivado, the code is generated with custom attributes and then constraints applied in the XDC output.
The created Verilog …