issues
search
YosysHQ
/
yosys
Yosys Open SYnthesis Suite
https://yosyshq.net/yosys/
ISC License
3.3k
stars
860
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
remove sorts from some optimisation passes
#4468
Ravenslofty
opened
3 days ago
2
rtlil: Fix `addShiftx` for signed shifts
#4467
povik
closed
2 days ago
0
Unable to code FSM into binary format
#4466
titan73
opened
1 week ago
0
Test build against upstream ABC
#4465
povik
opened
1 week ago
1
support error for Aggregate Initialization and Replication
#4462
yelen103
opened
1 week ago
1
Redo internal cell memory layout
#4461
widlarizer
opened
1 week ago
17
Make C++17 compiler required
#4460
mmicko
closed
4 days ago
4
Verific build support improvements
#4459
mmicko
closed
1 week ago
0
Yosys Synthesis Error: Hash Table Exceeded Maximum Size
#4458
LoSyTe
opened
1 week ago
8
CologneChip synthesis fails silently (simulation discrepancies)
#4457
tarik-ibrahimovic
opened
1 week ago
1
Feature Request: Add Support for Input Filelist -f Option
#4456
tarik-ibrahimovic
opened
1 week ago
1
peepopt: limit padding from shiftadd
#4455
phsauter
opened
2 weeks ago
0
IDES4_MEM gowin module is missing
#4453
LaneaLucy
opened
2 weeks ago
2
peepopt: avoid shift-amount underflow
#4452
phsauter
opened
2 weeks ago
0
`count_id(cell->name) == 0` failure
#4451
wyager
opened
2 weeks ago
1
fix bug of check-git-abc
#4450
nlwmode
opened
2 weeks ago
2
check-git-abc in Makefile for the first compile time
#4449
nlwmode
opened
2 weeks ago
4
peepopt shiftadd: Only match for sufficiently small constant widths
#4448
georgerennie
opened
2 weeks ago
1
system verilog "import" command not recognized (ERROR: syntax error, unexpected TOK_ID)
#4447
titan73
closed
1 week ago
3
Performance Issue: Synthesis Takes Too Long to Complete
#4445
LoSyTe
opened
2 weeks ago
9
Document script parsing
#4444
KrystalDelusion
closed
2 weeks ago
0
cxxxrtl: fix use of format specifiers in test
#4443
maribu
closed
2 weeks ago
0
Stub RTL Generation Feature
#4442
Peter-Herrmann
opened
2 weeks ago
0
Throws a segmentation fault if the 'input.blif' file's size is huge.
#4441
dmanjun5
closed
2 weeks ago
2
Update stale top comment in `ast.h`
#4440
povik
closed
2 weeks ago
0
liberty: Support for IO liberty files for verification
#4439
gatecat
closed
1 week ago
0
Clean up uses of #if(n)def EMSCRIPTEN
#4438
nakengelhardt
opened
2 weeks ago
0
rtlil.cc: Fix #4427
#4437
KrystalDelusion
opened
2 weeks ago
1
Ensuring smooth Yosys-to-Synlig compatability and tracking
#4436
chili-chips-ba
opened
2 weeks ago
13
cell reference names appear to be truncated
#4435
Cronus-38
opened
3 weeks ago
0
Fix memory leak in verific file parsing.
#4434
mikesinouye
closed
2 weeks ago
1
cxxrtl: capi: don't use deprecated invocation.
#4433
kivikakk
closed
2 weeks ago
5
cxxrtl: fix `debug_info()` deprecation message.
#4432
jfng
closed
3 weeks ago
0
smtbmc: Fix two .yw handling related crashes
#4431
jix
closed
3 weeks ago
0
Quote stripping in log command
#4429
KrystalDelusion
opened
3 weeks ago
0
haiku: Basic fixes to build under Haiku
#4428
kallisti5
opened
3 weeks ago
0
Yosys Verilog Parsing Error: Unable to Synthesize After Reading File
#4427
LoSyTe
opened
3 weeks ago
2
formal: Produced traces make it look like asserts trigger a clock step too late
#4426
NikLeberg
opened
3 weeks ago
7
sigmap: comments
#4425
widlarizer
opened
3 weeks ago
0
The $check cell could not support TRG_WIDTH > 1 lead to old design verification failed with `async2sync` command.
#4424
Readon
closed
3 weeks ago
2
Wrongly assign the name internal signal for vhdl
#4423
aniketabhiraj2004
closed
3 weeks ago
1
timeest: Add command for critical path estimation
#4422
povik
opened
4 weeks ago
1
clean up of wallace tree generation in booth multiplier
#4421
andyfox-rushc
opened
1 month ago
1
docs: add todo for $demux
#4420
widlarizer
closed
4 weeks ago
0
CXXRTL: >20x compile time regression with clang++-18
#4419
Wren6991
opened
1 month ago
3
cxxrtl: don't emit invalid code on unconnected outputs.
#4417
kivikakk
closed
2 weeks ago
0
fix(#4402):missing sign while for loop iteration variable is signed
#4416
YoYo-0513
opened
1 month ago
0
Update flake.lock
#4415
github-actions[bot]
opened
1 month ago
0
A topological loop is generated after using async2sync
#4414
ZhiyuanYan
opened
1 month ago
2
Yosys right shift error
#4413
WeneneW
opened
1 month ago
7
Next