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I have built IR from the latest armv9.4 model, but the configs do not appear to work.
For example:
```
$ ./target/debug/isla-footprint --arch /tmp/tmp.s5sMpblynE/outputs/armv9.ir --config confi…
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The instructions LD64B, ST64B, ST64BV and ST64BV0 can access more than 8 general-purpose registers and are therefore not safely handled by the [OP_xx fall-back](https://github.com/DynamoRIO/dynamorio/…
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I tried to create the 64 bit kernel, but I got an error.
```
input file: input.64
output file name: kernel_epep_64.hpp
conversion type: A64FX
error: unsupported vector type of B64 for A64FX
```
…
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This project is optimised only for SSE3 instructions? Are there any benchmarks for arm64 processors?
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https://tone.aliyun-inc.com/ws/xesljfzh/test_result/407720?tab=1
【环境准备】
```
BINARY_URL=oss://compiler-ci-bucket/dragonwell8/CI/tar/20241113-002913-606-#614-linux.aarch64.fastdebug.master-4e627…
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I guess these are the most used ARM cores on servers, so perfect for steamCMD.
```
# cat /proc/cpuinfo
processor : 0
BogoMIPS : 50.00
Features : fp asimd evtstrm aes pmull …
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There are some variable SIMD designs upcomming form [RISC-5](https://www.sifive.com/blog/risc-v-vector-extension-intrinsic-support) or [Arm](https://fuse.wikichip.org/news/4564/arm-updates-its-neovers…
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*Enhancement*
Hello, @std-simd
I would like to add SVE2 instructions via intrinsics/inline-assembly into std-simd to process data quicker, optimize the library.
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**Describe the Issue**
Mistral/Nvidia recently released [Nemo 12B](https://mistral.ai/news/mistral-nemo/) and llama.cpp have [added support](https://github.com/ggerganov/llama.cpp/pull/8579) for its …
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ARM has a rich set of SVE instructions[1]. For clients that need to instrument memrefs (e.g. drcachesim), we need to expand them to scalar loads and stores, like what we did for x86 scatter/gather in …