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Currently the `Yosys` [non-standard attributes](https://github.com/YosysHQ/yosys/blob/master/README.md#non-standard-or-systemverilog-features-for-formal-verification) `anyconst` `anyseq` etc are handl…
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This is my first attempt to synthesize a VHDL project using the yosys ghdl frontend. Per release instructions, GHDL synthesis should be available. I am setting the GHDL_PREFIX environment variable to …
fm4dd updated
3 years ago
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Have spent a week on this so far. Cat() not behaving as i expect when i use slices Cat_object[slice] ...
Have tried a number of permutations ... assigning to a slice ... Cat_object[n].eq(rhs) or…
scted updated
3 years ago
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@Paebbels I see you have modified compile scripts. Why have you removed support for compiling UVVM_VIP_WISHBONE from `compile-uvvm.sh`?
The script also does not work by default
```
Loading envi…
m-kru updated
3 years ago
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Hi. I am adding support for `ghdl --synth` and `ghdl-yosys-plugin` into [PyFPGA](https://gitlab.com/rodrigomelo9/pyfpga). I have some questions about ghdl-yosys-plugin.
I have four files:
* `blink…
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**Description**
It looks like GHDL might not like something like:
```
:= resize(to_unsigned(0, 1), 32);
```
```
unhandled (static) function: IIR_PREDEFINED_IEEE_NUMERIC_STD_RESIZE_UNS_NAT
``…
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Hi,
Pulling latest ( commit `163bb07`) results in a failure when building.
Steps to reproduce
```
git clone https://github.com/alpin3/ulx3s/
cd ulx3s
make build
```
It looks like an e…
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Hi, I have some questions regarding object files
1. Can I get netlist back from object files ?
2. Can object files be somehow interpreted by any synthesis tool ?
3. Can we use object files for se…
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Hi. I am not sure about to post it here or at the Yosys repo, but a first glance, it seems related to deal with VHDL packages. Let me explain.
* I was adding `ghdl-yosys-plugin` support into [PyFPG…
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Hello @mithro and @eine.
I think that you both know very well the FOSS ecosystem, but I know that you have predilections :P (Verilog and VHDL, of course). Would you check the following categorized …