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I am using pocket-extras-vectrex-v2.5.1. I have the bitstream.rbf_r in the obsidian.Vectrex-Extras folder. I have the ROM set from Archive. When I run a .json file the correct overlay loads, but the s…
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Hello,my analogue pocket os version is v2.1
But i found there was only normal display mode supported when i was playing games on openfpga gba core platform.
I can’t fix it
Thank u very much if u c…
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### Core Author username
rolandking
### Core .yml snippet
```yml
cores:
display_name: Athena SNK 1986
repository: openFPGA-Athena
```
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With openfpga, is there a way to get a required fabric corresponding to a given RTL design?. In other words, my tool input will be a verilog design and tool should output fpga fabric that can fit the …
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Feel free to close this, but just in case it wasn't documented.
The version info on the 0.20.0a release is still set to 0.17.0 and the date is still February in the core json files.
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**Is your feature request related to a problem? Please describe.**
Driven by the intensive needs on routing architecture, there is a trend that the feedback connections are moved to global routing, i…
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**Describe the bug**
The updater doesn't download Vectrex Overlays.
The openFPGA-Vectrex core doesn't include them.
https://github.com/obsidian-dot-dev/openFPGA-Vectrex
In the notes it says to…
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Dear Tangxifan,
I have encoutered an issue when running 3 ram in openfpga. Some bits of input signals of 3 ram are X as the picture below
![10](https://github.com/lnis-uofu/OpenFPGA/assets/9697424…
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There is a bug that puzzles me a lot, and OpenFPGA does not raise any error while the bitstream seems not correct.
I have a name.blif file, and its contents are as follows.
```blif
# Generated by Y…
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There are several methods available to secure FPGA IP designs for end-users. These include single-key encryption, where the bitstream is encrypted using a single key and decrypted at the FPGA/SoC side…