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Setting both EN_HLS=1 and EN_PR=1 leads to a synthesis issue.
Steps to reproduce for Alveo U200 (but I guess it does not work on any platform):
```sh
cd hw
mkdir build
cd build
cmake .. -DFDEV…
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Hi Kishore,
Recently, we tried to convert the generated bitstream to .mcs file and flash it in the QSPI flash inside Alveo U200. However, this made the entire machine fail to boot until we reverted…
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Hello,
I’m very interested to know whether this project can be used on Xilinx Alveo U50 and U250 FPGAs. In hdk_setup.sh file, I noticed that the program will download SH_ CL_ BB_ routed.dcp, whe…
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Hi everyone,
I met the problem as the title shown when I try to connect FPGA to host PC.
The environment is:
FPGA: Alveo U200
Vivado 2020.2
Ubuntu 20.02
error report:
sudo ./load_driver.sh …
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Hi team,
I am using Opennic design in alveo u200 and I am trying to enable auto-negotiation in the cmac_usplus_0 component. But encountering issues with bitstream generation. The following error mes…
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Hi @alexforencich ,
First of all, thank you for sharing this wonderful library.
I want to implement this project on Alveo U200 card. I follow verilog-ethernet/example/AU200/fpga_10g/README.md,
run…
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Hi,
I had tried to run PipeCNN on Xilinx Alveo U200, I'd modified Makefile and config file for U200 and TEST_CASE_1, but it's not worked for HW-Emulation (SW-Emulation is working).
Modified PipeCN…
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Hi @hst10 , may i know ur pylot support one tranied NN model from pytorch to hls code process for U200 board? if yes, how to set up this env. thanks
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![vitisai_onnxruntime_issue](https://user-images.githubusercontent.com/45734995/106882788-2c42ba00-6705-11eb-87f2-ff25ba3b3c9d.JPG)
Hello Team,
I am facing a Issue while trying to Inference the Cu…
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Hello,What version of Vitis AI supports U200?Vitis AI3.5? or all?