doonny PipeCNN issues - Githubissues

doonny / PipeCNN

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

Apache License 2.0

1.22k stars 370 forks source link

issues

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Error: incorrect setting of parameter VEC_SIZE !!!

#180 Muvyt opened 11 months ago
0
./run.exe conv.xclbin: terminate called recursively

#179 chu-chiao opened 1 year ago
0
Unable to make file for project_xilinx

#178 Muvyt closed 1 year ago
0
project_xilinx HardWare on U200 get a poor performance

#177 zyt1024 opened 1 year ago
0
Make host error, no opencl header files, ZCU102/Vitis/Xilinx

#176 qiuzeyu closed 1 year ago
5
Software emulation OpenCL runtime error,can not return a result in executing Layer 1, Xilinx/Vitis

#175 zhangxian314 opened 1 year ago
0
Resnet Error on zcu102

#174 vijaydhoki opened 1 year ago
0
Software emulation OpenCL runtime error, Xilinx/Vitis

#173 sysuresh opened 2 years ago
2
Possibility of running on 3rd party board

#172 jimmy-adams opened 2 years ago
1
Integrate the similar module mult_add_fix8bx4 into the system.

#171 WeipingXiao1412 opened 2 years ago
1
Unable to download Data set

#170 Crips2013 closed 2 years ago
2
How to debug from the code.

#169 TranQuocVietUIT opened 2 years ago
1
make fpga error for xilinx

#168 justinjiaxinghu opened 2 years ago
14
How to caculate Coefficients lookup table for lrn computation

#167 datnguyen263 opened 2 years ago
0
Need information about your project !

#166 TranQuocVietUIT closed 2 years ago
1
Running PipeCNN on U200

#165 Alsumbjip opened 2 years ago
7
How to fix Wrong Results with Board De1Soc

#164 datnguyen263 closed 2 years ago
2
In YOLO

#163 ppphj opened 3 years ago
0
data_test1.dat file

#162 dheeraj141 opened 3 years ago
0
How can i run this project in ZCU102 with SD card?

#161 zhaobr340104 closed 3 years ago
3
how to libalteracl.so library problem

#160 GUUTA opened 3 years ago
0
docs: fix simple typo, temperary -> temporary

#159 timgates42 closed 3 years ago
0
how to config addition_precision_config in layer_config.h

#158 WenyeLiu opened 3 years ago
2
ModelZoo link is broken in User Instructions

#157 Lissanro closed 3 years ago
3
Question about software simulation

#156 zjuchensa closed 3 years ago
1
How to get FPGA power consumption?

#155 tommygyl closed 3 years ago
1
Failed to get device name size

#154 davidtong-300 closed 3 years ago
3
An error when compiling the project

#153 davidtong-300 opened 3 years ago
3
how do I solve wrong result ?

#152 GUUTA opened 3 years ago
2
CONV_GP_SIZE_X vs WIN_BUF_SIZE

#151 justinf2 opened 3 years ago
0
CL_OUT_OF_HOST_MEMORY on Arria10 SoC platform

#150 WenyeLiu closed 3 years ago
0
Image Data Set

#149 floralfa opened 3 years ago
0
How o I fix this error: Allocate memory for data and weights failed !

#148 GUUTA closed 3 years ago
0
PipeCNN for Xilinx

#147 nazarihome closed 3 years ago
2
"Error" aocl program

#146 sergio14890 closed 3 years ago
1
how do I solve this problem undefined reference to `clCreateContext'? I use OS Ubuntu 18.04

#145 GUUTA closed 3 years ago
1
OPENCV libraries for arm

#144 sergio14890 opened 3 years ago
19
De1-SoC Performance Different from Example Given !

#143 mingyi136 opened 4 years ago
8
Design does not fit into Cyclone V on DE10-Nano

#142 kutenai opened 4 years ago
1
yolo make file and missing files in host directory

#141 kutenai opened 4 years ago
2
Cannot find board_env.xml in /intelFPGA_pro/19.1/hld/board/a10_ref，How can I fix it? Please

#140 JDse7en closed 4 years ago
2
When I try to change num_compute_units the following error generated. What is cause this? and how I fix it?

#139 GUUTA opened 4 years ago
2
When i try to make file the following error was generated. How I can fix this problem?

#138 GUUTA opened 4 years ago
7
quartus_map ended unexpectedly

#137 Alhad1994 closed 4 years ago
5
model used?

#136 mAxwong1014 closed 4 years ago
2
version `GLIBC_2.17' not found (required by ./run.exe)

#135 sergio14890 closed 3 years ago
12
while making error- aoc command not found

#134 HemantaIngle closed 4 years ago
2
Compilation de1soc board

#133 sergio14890 opened 4 years ago
13
mean.data format

#132 mAxwong1014 opened 4 years ago
6
RTL synthesize BUG about DSP and LUT

#131 tommygyl opened 4 years ago
8