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Hi, this project seems great as a starting point for open-source DDR PHY, especially for the ASIC flows.
However, the mixed-mode components, which are the most important parts of PHY, seem yet to b…
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**Issue by [whitequark](https://github.com/whitequark)**
_Thursday Aug 22, 2019 at 21:49 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/184_
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A number of people have express…
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It would be useful to have table of the different models.
Currently it's quite confusing if you're unfamiliar with the project. E.g. this repo shows the bitaxeUltra as the most recent version, wher…
Sjors updated
3 months ago
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### Feature Description
I'm interested in running designs through sc using standard commercial ASIC tools (in title).
## Steps Taken
* I did a few `grep -R` text searches on the repo looking…
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I couldn't find a better issue to discuss this. RandomJS is _not_ ASIC-resistent. An ASIC designer may simply design a chip to do compilation. In effect, your PoW is a compiler, which is definitely…
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Hi,
I have read your recent journal but cannot really understand the step to do the GL test and get the output render frames. I am quite novice in the ASIC workflow.
To be able to do this test woul…
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Hello,
When static FDB entries are added by user (using Adapter Host, eg: SONiC), is the SAI adapter expected to invoke the fdb event notification function? Or is event notification to be used only…
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WDYT? Is this publication in scope?
```
@inbook{Kulikowski_2006,
author = {Kulikowski, Konrad J. and Karpovsky, Mark G. and Taubin, Alexander},
booktitle = {Fault Diagnosis and Tolerance in Cryptogr…
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https://github.com/SChernykh/CryptonightR/issues/1#issuecomment-452775046
> In fact, a carefully designed ASIC could still outperform GPU by spending more resource/area on the bottlenecks. The memo…
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**Goals**
- [x] extract S-curve on Pixel 0 with max stat and cardboard and see and document the impact
- [x] probe dnn and dnn
- [ ]- ideally get a hold on a new scope with 4 working chan…