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Hi
How difficult would it be to have support for the baremetal cortex-m7 + hard float?
Thanks
mathk updated
4 years ago
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The Data Cache for Cortex-M7 devices is currently disables, due to a lack of in-depth understanding of cache policies during porting. The Instruction Cache however is enabled, since it only gets read.…
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We may want to avoid expressing FPU extensions in ARM Cortex-M CPU constraints.
# Proposal
Refrain from extending the set of `@platforms//cpu:armv*-mf` constraints, and annotate the existing const…
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This will possibly increase the performance of our applications (pjsip, opencv, etc.). In stm32 cube you can search for `CPU_CACHE_Enable`. But enabling of these caches may lead to instruction and dat…
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> For Cortex-M4/M7 with FP the thread context requires 200 bytes on the local stack. For these devices the default stack space should be increased to a minimum of 300 bytes.
In my application only …
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related to #61, as I already spotted some instances of compressible but `.w` instructions used in some inputs, "for no reason".
Certain microarchitectures may suffer performance degradation due to …
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**I confirm this bug has not already been reported**
- [X] I have searched the issues and this bug has not been reported previously
**Describe the bug**
I pulled the tip of git, then ran quicke…
popey updated
1 month ago
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**Describe the bug**
I use ThreadX on a system with **cortex_m33** core with proposed CMAKE construct to compile ThreadX into a lib. But confusingly the file **tx_initialize_low_level.S** with some f…
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```toml
[build]
target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU)
target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU)
```
which also requires the u…
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### Zig Version
0.14.0-dev.2051+b1361f237
### Steps to Reproduce and Observed Behavior
`zig targets | grep cortex`
zig targets | grep cortex
"cortex_a12": [
"cortex_a15": [
"cortex…