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### Checklist
- [x] Did you write out a description of the feature you want to see?
- [x] Did you look around for any related features?
- [x] Did you specify relevant external information?
###…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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ARTIFACTS (.v) files not being generated after running after invoking the command- "rtl -a /demo/arch/pynqz1.tarch -s true" the RTL Summary is generated but not the .v files
OS- Windows 10
Errors:…
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What is the internal structure of firrtl-interpreter and what is the model? How to change the signal inside the model(poke or peek)? Can someone explain it? See the source code or do not understand.
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The FullAsynchronousResetTransform no longer removes its annotation, which can lead to problems where the pass is no longer idempotent. It seems like some work has gone in to minimizing the amount of …
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FIRRTL spec only covers this for modules, and use on extmodule's in untested and unverified.
The following parses and compiles fine:
```firrtl
FIRRTL version 4.0.0
circuit EL:
extmodule X…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
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I use the following codes to generate verilog using this repository as template:
```scala
object myMultipierMain extends App {
val path = "~/project/CPU/playground/generated"
val firtoolOption…
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Hi, I'm just starting to test out chiffre and I was trying to setup the sample LeChiffre configuration. I ended up having to change the patch file, but now I am getting this error and I don't have an…