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Hello,
I have added some extra layers on a CIFAR-10. I managed to make a successful simulation of the model and execute software inference on PYNQ board. However if I try to run HW acceleration the …
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> [!IMPORTANT]
A proposal will go through a review process by a PSE to ensure the quality of the task and alignment with the acceleration program mission. Please be patient and wait for the review to…
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Hey all,
I am working on controlling motors with a FPGA. You can see my working setup [here](https://youtu.be/-0uB2MydtrE) .
The video is not the greatest but it shows where I am at. Code for th…
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With the possibility of implementing non-GPU hardware acceleration remove the word GPU from API and keywords.
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Hi,
I am trying to upgrade from Centos 7 (kernel 3.x) running the old altera spi edition for FPGA BMC communication, to a debian 12 testing (Kernel 6.5) with OPAE build from github master. The car…
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Dears, this issue for more decision about how can we cover the vRAN or/and any workload required the same requirements ( FPGA ) at the edge, we agreed during Edge meeting that we need to have a new pr…
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Hi, All:
I have some questions about how to enable cfu.v in litex.
1. for currently CPU support, it seems VexRisc-V only, not for VexRisc-V SMP.
2. from current project samples, the CFU functio…
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Can I please ask if you think it viable to use your J1 code to create a GA like device in FPGA? Would it, in your opinion, be a massive amount of effort?
My hope would be to use something like the …
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Hi,
I came across your design as I am looking for a Ethernet design with UDP listener to be implemented on FPGA. I have a Alveo u50 card installed in my machine. I was able to generate the bitstrea…