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In the verilog example user design (`sequential_16bit_en.v`), the value assigned to `io_oeb` is `28'b1`.
However, if the resulting bitstream is uploaded to a fabricated eFPGA, this will cause that th…
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When I did `git clone --recursive` on this repo, I actually ran out of disk space on a disk with ~25GB free. How large a disk do you recommend for downloading this PDK?
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You mentioned that the PDK is specially made for RF designs. But there are no Transmission Line, Balun or Transformer for both simulation and layout. How can I use transmission line when designing the…
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The PFC460 and PGS134 are available in a SOP24 (300 mil) package. It would be nice to have a board supporting these powerful devices.
spth updated
8 months ago
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Dear Jakob
I've successfully run the project on IIC-OSCI-TOOLS,and the RL_placement is done,I have got the DiffAmp_placement pkl file.However, when I try to open this pkl file in magic tools,as you…
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The README mentions "Use SDCC 4.1.0 to build. Later versions create broken code". What is the problem here? Is there a corresponding ticket in the SDCC bug tracker?
spth updated
6 months ago
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KLayout 2.9.6
2 different GatPoly should have 180nm or 250nm distance. but there is no DRC error at 70nm.
im not sure what the correct minimum is in this case:
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How can I find the methods to handle the mTLS connection?
Best regards,
Lorenzo
lgtti updated
8 months ago
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### What Versions are you running?
OS Version: Mac OS 12.5.1 (21G83)
VSCode Version: 1.71.2
Puppet Extension Version: v1.4.0
PDK Version: 2.5.0
### What You Are Seeing?
No Intellisen…