FPGA-Research-Manchester FABulous issues

FPGA-Research-Manchester / FABulous

Fabric generator and CAD tools

https://fabulous.readthedocs.io/en/latest/

Apache License 2.0

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issues

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Vhdl synthesis

#202 Biswajitks1 opened 15 hours ago
3
Switch-Matrix contains commented-out ports

#201 hoyer-ims opened 4 days ago
2
Synthesis of VHDL

#200 Biswajitks1 closed 5 days ago
3
:fabric_gen: Fix VHDL ConfigMem gets instantiated twice per tile

#198 EverythingElseWasAlreadyTaken closed 1 week ago
7
FABulous_API.py Documentation

#197 A-Kibats opened 2 weeks ago
7
init commenting

#194 A-Kibats closed 2 weeks ago
1
fabric_generator:file_parser: Refactor parseFileVHDL and parseFileVerilog

#177 EverythingElseWasAlreadyTaken opened 1 month ago
7
README+Docs: Add virtual environments as recommended usage way

#176 EverythingElseWasAlreadyTaken closed 2 weeks ago
14
Removing VPR support

#175 KelvinChung2000 opened 1 month ago
0
Adding back the line that is deleted by mistake

#174 KelvinChung2000 closed 1 month ago
0
Refactor file paths and imports in FABulous code

#173 KelvinChung2000 closed 1 month ago
11
Splitting FABulous.py into API file and CLI file and clean up import

#172 KelvinChung2000 closed 1 month ago
0
Refactor file path handling in fabric_gen.py using pathlib

#171 KelvinChung2000 closed 1 month ago
0
Fix file path issues in fabric_gen.py and FrameStrobe problem

#170 KelvinChung2000 closed 1 month ago
0
Fix file path issues in fabric_gen.py

#169 KelvinChung2000 closed 1 month ago
0
Configuration FrameStrobe Widths

#168 RobB720 opened 2 months ago
4
Add documentation of MID wires

#167 IAmMarcelJung closed 1 month ago
4
One-hot Mux Implementation

#166 RobB720 opened 3 months ago
5
Mux input ordering

#165 RobB720 opened 3 months ago
8
Improve and fix problems in geometry generation

#164 JakobTernes opened 4 months ago
3
Add formatter

#163 KelvinChung2000 closed 2 months ago
11
Question: Clock distribution

#162 mole99 closed 4 months ago
4
Fix FrameData wiring for NULL tiles at the border

#161 mole99 opened 4 months ago
0
Missing configuration for CPU_IO

#160 mole99 opened 4 months ago
2
Package and Publish to PyPI

#159 mole99 closed 4 months ago
2
Code Formatter

#158 mole99 opened 4 months ago
2
Orientations of basic tiles

#157 mole99 opened 4 months ago
0
Improve CI

#156 mole99 opened 4 months ago
0
Merge Verilog and VHDL project templates

#155 mole99 opened 4 months ago
4
Separate fabric and tile configuration

#154 mole99 closed 4 months ago
2
VHDL generation broken

#153 mole99 opened 4 months ago
0
Print traceback on error inside FABulous Shell

#152 mole99 closed 4 months ago
2
FABulous.py + multiple verilog files in the user_design

#151 ruck314 closed 4 months ago
3
FABulous API

#150 mole99 opened 4 months ago
4
Separate Fabric and Tile description

#149 mole99 opened 4 months ago
1
Exception messages not printed

#148 IAmMarcelJung closed 4 months ago
2
Workflow fail silently

#147 KelvinChung2000 opened 5 months ago
2
Use pathlib to extract the file name information

#146 IAmMarcelJung closed 5 months ago
0
synthesis error

#145 anudeepdharavathu opened 5 months ago
1
Correct bel.txt comment

#144 TaoBi22 closed 5 months ago
0
Different tile coordinate system in Documenation and bel files

#143 IAmMarcelJung closed 5 months ago
2
"eFPGA_top" parameters for larger fabric

#142 anudeepdharavathu opened 6 months ago
4
Fix small typo in the documentation

#141 IAmMarcelJung closed 7 months ago
1
Missing documentation of MID wires

#140 IAmMarcelJung closed 1 month ago
2
What do NN, EE, SS and WW stand for?

#139 IAmMarcelJung closed 3 months ago
5
Implement a simulation command in the shell (only for verilog)

#138 IAmMarcelJung closed 1 month ago
4
Fix rendering of simulation doc commands

#137 TaoBi22 closed 7 months ago
0
Fix outdated simulation docs

#136 TaoBi22 closed 7 months ago
0
Add pycache dirs to git ignore

#135 TaoBi22 closed 7 months ago
0
Non exisiting directory in documentation of the simulation

#134 IAmMarcelJung closed 7 months ago
3