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**Describe the bug**
When attempting to create a RISCV version of the Linux Kernel v6.11.3, the kernel panics due to an illegal instruction.
**Affects version**
gem5 24.0.0.1
**gem5 Modificat…
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**Describe the bug**
The execution result of the riscv vector slide instruction is not as expected. The picture of trace here shows the bug. (vlen=128)
The results in trace do not conform to the d…
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**Describe the bug**
gem5 throws a `panic: panic condition !pte occurred: Tried to execute unmapped address 0.` when we try to restore a saved checkpoint in SPARC isa. The saved checkpoint is of runn…
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I have implemented a GEMM kerenl using RVV and complie it into a bare metal using AM. Before simulation, I deleted the function calls that were not aligned with the RTL and depended on the vector dest…
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### What happened?
We use artifacts to run tests on our GitHub organization. Sometimes randomly the atrifact download would fail randowmly with the following error.
```
error: Unable to downloa…
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I replaced the [memory config line of code](https://github.com/gem5/gem5/blob/e8bc4fc137a5a7e82b601432271a027b652ae69b/configs/example/arm/starter_fs.py#L111) in the starter full-system simulation for…
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**Describe the bug**
Gem5 cannot set the locale to `C.UTF-8`, gem5 appears to only support `C` locale, and also defaults to it, while native hardware appears to default to `C.UTF-8`.
**Affects ver…
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when following README instructions to drive the simulation with gem5:
https://github.com/antmicro/xls-cosimulation-demonstrator?tab=readme-ov-file#run-gem5
it currently hangs on:
```
xls-cosimulation-…
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Hello!
I was wondering if WA integration with Gem5 is still supported:
http://old.gem5.org/wiki/images/b/b8/Summit2017_wa_devlib.pdf
And if so would you be able to point me to a link where it …
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Hi, I'm working on running SPEC06 checkpoints on XS-GEM5, and I notice that the default L2 hardware prefetcher is WorkerPrefetcher in the script simple_gem5.sh:
https://github.com/OpenXiangShan/GEM5/…