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Allow parsing handles with parameters, e.g.
https://hdl.handle.net/11471/513.30.3?index=3
Currently only ?format=json parameter is allowed for handle, implement generic solution allowing variati…
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For example, an image was transferred:
![image](https://github.com/Martichou/rquickshare/assets/48642222/f96912ed-5c7d-431f-b7b6-24cb9fa0bacc)
Clicking "open" navigates to a new browser tab, in …
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```typ
#slide[
== Title
#columns(2)[
+ airhdl
+ AGWB
+ AutoFPGA
+ Cheby
+ Corsair
+ FPGA Vendors
+ hdl_register
+ II & CII
+ IP_XACT
+ Opentitan Register Tool
+ Register Wizard
+ RgGen
…
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Hi, all!
Is it possible to use cv2.findContours() with Vitis vision Library?
1. I didn't find this function in list:
https://github.com/Xilinx/Vitis_Libraries/blob/master/vision/docs/src…
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I'm interested in creating a PAC crate for a chip that only seems to have RTL files available (https://github.com/T-head-Semi/openc910).
Is there any way to convert these files to SVD, and then use…
rmsyn updated
9 months ago
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It would be awesome to have better FPGA support in the [repo for bazel_rule_hdl](https://github.com/hdl/bazel_rules_hdl). Would you be interested in collaborating on that?
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There are a bunch of Googler's working on Bazel rules for hardware at https://github.com/hdl/bazel_rules_hdl -- this is uses by Google's HLS toolchain called XLS (https://github.com/google/xls).
Th…
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Hi there,
Currently I am trying to synthesize PICORV32 onto DE0 Nano FPGA using Quartus Prime Lite.
I have no problem synthesizing with [synth_area_top.v](https://github.com/YosysHQ/picorv32/blo…
YapWC updated
1 month ago
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have updat…
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#### Feature request description
Currently Sourcegraph doesn't support syntax highlighting for Verilog and VHDL.
![image](https://user-images.githubusercontent.com/94965293/143841769-5fb4e571-1ae…