issues
search
Lightelligence
/
rules_verilog
Bazel build rules for compiling Verilog
Other
18
stars
7
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
Massive update from other branches
#60
justin371
opened
4 months ago
0
PCIe IP integration with lots of .h files
#59
justin371
opened
1 year ago
0
simmer update to ignore I/O errors when grep'ing log file
#58
jmlemay99
closed
1 year ago
0
simmer bug fix for pre_run flow
#57
jmlemay99
closed
1 year ago
0
Fhan/compile pldm sa
#56
FuqiangHan
opened
1 year ago
1
performance and debug command line args for xrun
#55
jmlemay99
closed
1 year ago
0
Lw/simresults update
#54
justin371
opened
1 year ago
0
dv_tb compile order change
#53
jmlemay99
closed
1 year ago
0
update the coverage options for the re-sim with the same seed
#52
justin371
closed
1 year ago
0
Fhan/compile pldm ice
#51
FuqiangHan
closed
1 year ago
0
removing top declaration from cadence dv tb compile template
#50
jmlemay99
closed
1 year ago
0
support for a new dv_tb attribute for specifying verilog config files
#49
jmlemay99
closed
1 year ago
0
remove the unused options
#48
justin371
closed
1 year ago
0
adding support for xrun -makelib compile flow
#47
jmlemay99
closed
1 year ago
0
simmber bug fix comparing --parallel-max
#46
jmlemay99
closed
1 year ago
0
simmer bug fix related to parallel-max comparisons
#45
jmlemay99
closed
1 year ago
0
inital creation of CODEOWNERS
#44
jmlemay99
closed
1 year ago
0
Set up pylint as a CI Action
#43
ciglass
opened
1 year ago
0
simmer libs and executables
#42
jmlemay99
closed
1 year ago
0
fix the cov_opts issue that None type cannot be anded with the string opt…
#41
justin371
closed
1 year ago
2
simulator.bzl explicitly depends on runmod
#40
ciglass
opened
1 year ago
0
simmer updates for xrun fsdb
#39
jmlemay99
closed
1 year ago
0
Fix the fsdb wave dump via XRUN
#38
justin371
closed
1 year ago
0
lint parser python library update
#37
jmlemay99
closed
1 year ago
0
Attempt to force GitHub to recognize .bzl and BUILD files as Starlark
#36
ciglass
closed
1 year ago
0
Look into doing automatic flist generation for Verdi
#35
ciglass
opened
1 year ago
0
Consolidate verilog_dv_tb vcs/xrun attributes
#34
ciglass
opened
1 year ago
0
remove per-simulator flist files, adding static compile args to templates
#33
jmlemay99
closed
1 year ago
0
Look into build configurations to choose tool versions
#32
ciglass
opened
1 year ago
0
VCS flow integration
#31
justin371
closed
1 year ago
1
Add diff check for defs.md
#30
ciglass
opened
1 year ago
0
Integrate the VCS flow
#29
justin371
closed
1 year ago
4
Lw/vcs integrate
#28
justin371
closed
1 year ago
0
Document lint waiver usage
#27
ciglass
opened
1 year ago
0
Implement code block lint waivers for HAL
#26
ciglass
opened
1 year ago
0
Implement lint rule waiver abstraction
#25
ciglass
opened
1 year ago
1
Ascent requires different defines format
#24
ciglass
opened
1 year ago
0
Add support for Ascent Lint
#23
ciglass
closed
1 year ago
0
Move lint parser scripts to vendor directories
#22
ciglass
opened
1 year ago
0
Fixed bug where lint_parser_hal used 'is' incorrectly
#21
ciglass
closed
1 year ago
0
Bump cookiecutter from 1.6.0 to 2.1.1
#20
dependabot[bot]
closed
2 years ago
0
Consider merging / contributing to hdl/bazel_hdl_rules?
#19
mithro
opened
2 years ago
3
Converted verilog_dv_test_cfg to output everything in *_dynamic_args
#18
ciglass
closed
2 years ago
0
Fixes for bugs introduced in release v0.0.10
#17
ciglass
closed
2 years ago
0
Added options for RTL unit test to render waveforms. Refactored RTL tests to use template files
#16
ciglass
closed
2 years ago
0
Add licqueue option to Xcelium svunit template
#15
wstucker
closed
2 years ago
0
Add timeout option to verilog_dv_test_cfg
#14
wstucker
closed
2 years ago
0
vcs flow integration
#13
justin371
closed
1 year ago
2
Lw/vcs
#12
justin371
closed
2 years ago
1
Refactored CDC arguments to better match common use cases
#11
ciglass
closed
2 years ago
0
Next