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The install docs (https://github.com/tinyvision-ai-inc/UPduino-v3.0/blob/master/docs/source/getting_started/tool_installation.rst) mention that a fork of apio may be required. I thought I would check …
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Hello,
can you please add support for icebreaker board?
it's ICE40 based open hardware board readily available for reasonable price through several vendors.
It's also fully documented here: https:/…
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A board is considered supported when the board boots with micropython -- which needs;
* LM32 and RISCV processor booting
* SPI flash execution
* UART
Ideally the following are also supp…
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The BIOS does not compare up on the Lattice ice40 HX8K EVB. There are several issues.
I have gotten some of the way here:
https://github.com/niklasnisbeth/litex-buildenv/commit/846fc6193972692f9…
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A new DIOT/EEM version is on the way:
- take the existing design and replace CPLD with ICE40 - circuit and EEM connectivity copied from Fastino-DIOT (with proper power sequencing)
- get rid of LVDS …
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Hello, can you please publish bitstream for ICEBREAKER board?
It seems to be opensource and extremely well documented:
https://github.com/icebreaker-fpga/icebreaker
Also you already support oth…
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I have a design that fails initial placement. This is mostly because of incompatible CE lines for the flipflops and it is for a LP384 which doesn't have a lot of resources and I'm trying to pack 330 L…
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Apio has two commands to verify the code, 'apio lint' and 'apio verify' and this is confusing. I am looking into consolidating both of them into a single 'apio lint', possibly with a flag to achieve …
zapta updated
1 month ago
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Dear,
can anyone help me using BRAM 512 word, 16 bit as a ROM (RAM preloaded during FPGA power on)
using GHDL VHDL -> Yosys -> Lattice ICE40 FPGA please ?
Greetings,
Patrick
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Thanks for all the hard work making this package available.
I installed only one package with the command `pip install yowasp-nextpnr-ice40-8k`, on Windows 10 x64, Anaconda Python 3.7 (same result …