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Hello,
I'm following the Getting Started Guide and I tried to run "make cml_core" as they explained, but I get these errors:
make -C tools/scripts
make[1]: Entering directory '/home/martu24/NetFPGA…
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Hello community,
I've been trying to synthesize the vicuna vector coprocessor for Kintex7 FPGA (Genesys2 Board).
Wherein I've created a **_vproc_config.sv_** package file using command -
make …
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There are 3 main mantle targets:
-- boards (ice40, altera, etc.)
-- CoreIR
-- Verilog (not heavily used)
There are 3 main compilation outputs:
-- Verilog
-- CoreIR
-- CoreIR-Verilog
I beli…
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Hi @unbtorsten, @jrrk2,
I just saw that there are now two pull requests from both of you
open for prjxray:
https://github.com/SymbiFlow/prjxray/pull/1844/files
https://github.com/SymbiFlow/prjxra…
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hello
I want to impletement ATA to SATA interface?
```
Can I use your project?
```
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Hello,
This is a great project, and I am quite sure that I am not the only person closely watching it. MiSTer is awesome, but it has some shortcomings:
- you have to take additional actions to m…
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I have a board with kintex7 part in it. What i can use is single gtwizard ip rather than gtwizard_ultrascale IP that most of the examples utilize. I would like to ask for advice on how to migrate to a…
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以前のKintex7版のほう、順調に動いているのですが、ときどき、以下のような縦縞が入ることがあります。
https://www.dropbox.com/s/dbvn3w914u5pg6q/2017-12-15%2017.46.34.jpg?dl=0
一度入ると、なかなか消えず、カメラ、FPGAの電源を入れなおして、消えることもあれば、消えないこともあって、という感じです。なんとなくですが、ず…
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## Issue Description ##
The X3x0 of USRP 2974 is not discoverable in Vivado 2015.4/2019.1. But appears in lsusb as FTDI.
## Setup Details ##
The block diagram of USRP 2974 suggests that the SoM…
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This issue is a reminder to regularly review code and
- push tested code to upstream projects where possible.
- separate i) system requirements (readily available from upstream), ii) customization …