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Especially RISC-V64.
There is some expectation of adding support for the new RISCV architecture, even though it is an emulated environment for example QEMU.
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### Check for existing issues
- [X] Completed
### Describe the bug / provide steps to reproduce it
Simple, if you have a computer with a weird CPU arch (i got a riscv SBC): try to `ssh` using zed i…
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Some aarch64 machines (typically consumer machines that may need support for 32-bit apps) support 32-bit instructions, others (typically servers) don't.
This is hard to express in the archpolicies[…
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### Is your feature request related to a problem? Please describe.
https://github.com/xmake-io/xmake/pull/5772
https://github.com/xmake-io/xmake-gradle/blob/bc64df881ccc09a77d89c2847c3c0ee64de7398…
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Hello. I've found a bug on my RISCV-64 environment.
I used GCC to build perfetto packages and my target environment uses GNU's libraries such as glibc.
Before copying the stack, the client hooking li…
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# Description
The below IR code compiles successfully on various architectures including AArch64, x86_64, ARM, Berkeley Packet Filter (BPF), NVIDIA Parallel Thread Execution (NVPTX64), PowerPC, and R…
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Hello,
I am encountering an issue when I used nx_packet_allocate because ULONG is considered to be 8 bytes for the RISCV-64 bits architecture.
It worked perfectly on my previous target CORTEX-R4…
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when I execute the command 'make qemu'
I meet the error is that "Truncation of relocation to fit: R_RISCV_PCREL_L012_I against '.L0"
I've commented out the code in the corresponding file, but simi…
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I'm frankly surprised that no one else has created an issue for this feature request yet.
Obviously, adding support for a different architecture is far from a trivial task, as we can see from the w…
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I have a generic tail-padding function:
```C++
inline vuint8m1_t tail_load(void const* data, size_t length) {
uint8_t const* ptr = reinterpret_cast(data);
vuint8m1_t v = __riscv_vle8_v_u8m…