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I have a Zybo Zynq 7000. If that is not easily supported by your tools, can you please provide a recommendation for any open source tools which might support it?
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I've been following the Zynq-7000 SoC Embedded Design Tutorial (2023.2) using a Digilent Zybo Z7-20. The cdma-app showed FAIL even though the DMA transfer occurred (I used the Memory inspector to re…
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Dear @btashton,
What are the IP cores should be added in Zybo Z7 platform which is already written in litex-boards( https://github.com/litex-hub/litex-boards)
Does generating the bitstream with…
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Create and test Petalinux distribution for "full" system. Use programmed device to test Linux functionality. Debug and update as needed.
**DOD**
- [x] Linux boots
- [x] CLI interface is availab…
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Can you consider to implement generic uio in your python periphery? As i see your MMIO implementation can serve the reg mapping for a /dev/uioX, only the IRQ waiting which is needed to implemented for…
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In order to access ZYBO Z7-20 without setting IP address manually, it is better to add a static IP address for eth0 as default in creating root file system.
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I am trying to implement the Canny edge detection in SDx 2017.4 using the release of 2017.4.
I imported the files in the folder Canny to do so, and I tried to solve some problems related to data type…
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Review major architectures and techniques that are hardware friendly:
- quantization
- binarization (full and partial)
- XNOR networks
**DOD**
- [x] chose network to implement on Zybo-Z7-20
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Hello, I'm trying to build PYNQ image for my Zybo Z7-10. As shown in the [link](https://discuss.pynq.io/t/3rd-party-images-for-zynq-boards/431) I'm using your projects. I would like to build PYNQ 2.5 …
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Can you help me find where the Results are sent to? I found that A and Z were mapped to pins in the Zybo-Z7-Master.xdc file, but I don't know where to find where Result0-7 are mapped to.
Also, I sa…