-
**Describe the bug**
Device drivers incorrectly configure accelerators with more that 4 configuration parameters. The p2p-related functions in the driver most likely have a buffer overflow.
**To R…
-
Hi can you guys tell me what data type is the file that gets written to the dma for the hardware accelerators found in the ad9361_fpga_signal_source.cc?
I’m thinking ibyte or ishort?
Thanks.…
-
# Add support for other SR-IOV devices
| Status | Proposed |
:-------------- |:---------------------------------------------------- |
| **Author…
-
**Issue:** As discussed in multiple forums, CNTT currently specifies hardware in multiple documents (e.g., RM, RA and RI), making alignment challenging. Further, when RI/CIRV (or CSPs) are procuring h…
-
Hi, all
#23917 introduces [Nvidia-docker](https://github.com/NVIDIA/nvidia-docker), it has provided a convenient way to use Nvidia GPU accelerator in container.
To use more hardware accelerators(e…
-
It's been great to see growth in the TVM community contributing to VTA in the recent years. VTA is TVM's open source hardware accelerator stack, and consists of multiple components bridging hardware a…
-
Need to support Autotuning DSL as part of the Application optimisations.
The DSL contains
•Tuning parameters can be defined, constrained and injected into application source, build or run
•Easy to …
-
Hi,
I've spent this week attempting to get this driver up and running with a KCU105 and a Jetson Xavier AGX with very mixed results.
I've built a number of variants and have been seeing some very …
-
I am wondering about the purpose of the memory pool abstraction and why it was necessary to write a custom memory management system for SEAL/HE. It seems it may have been more important before the imp…
-
Is it conceivable that there exists a HE scheme in which a computation can be decrypted by a server only after a predesignated series of operations have been performed?
Meaning to say, that someho…