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```
What steps will reproduce the problem?
1. Use r1.1 code with default voltage reference (1.1V)
2. Use a Witespy KV modded minimOSD board (22k/1k dividers)
3. Increase GUI calibration to max (255)
4…
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The scheduled loadshapes do not work properly. It appears that 'dt' does not initiate correctly (or is not calculated correctly at all) -- dt is often negative.
The whole class needs to be reviewed…
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The scheduled loadshapes do not work properly. It appears that 'dt' does not initiate correctly (or is not calculated correctly at all) -- dt is often negative.
The whole class needs to be reviewed…
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In my case studies, I need to compute the drt on low-frequency inductive loops.
Can you please comment on this prospect? I am not sure if it is feasible to modify the current version of EISART.
…
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-Undocumented arguments in wire method. What are they?
-Segment voltage and current? get_structure_currents () returns a unrecognized object. How to parse this?
-Feedpoint impedance?
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Per forum posts at:
https://sourceforge.net/p/gridlab-d/discussion/842562/thread/288d5b65/
https://sourceforge.net/p/gridlab-d/discussion/842562/thread/31deec3f/
Looking at the transformer code, …
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Hi, I'm using PrawnBlaster to generate pseudoclock for my NI 6535 board. The clock terminal is set to PFI4 by
```Python
NI_PCIe_6535(
name='ni_6535', parent_device=master_clock.clocklin…
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The doc infrastructure should be the same between ecto and the kitchen so we don't have impedance mismatch.
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Will weighted average across MGRAs to transit stops work? Use boardings from assignment as the weight. Use the impedance from the MRGA to stops as the measure.
-