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Hello,
I'm trying to add simple DMA device to the lowrisc (lowRISC 0-4 milestone release), I'm following the tutorial on the following link:
http://www.lowrisc.org/docs/internship-2016/device-tutori…
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Hi all,
I'm studying the **address map** of the u500vc707devkit. My question is about the Object **ConfigStringOutput**, which you define inside [freedom/src/main/scala/unleashed/u500vc707devkit/T…
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Hi all,
I'd like to ask something about the UART in the U500 platform. In particular:
1) At which clock does it operate? Think about the process inside file:
freedom/fpga/u500vc…
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- `ref_clk` distribution
- rf backplane
- amc backplane
- `dac_clk` generation
- `sysref` generation
- by FPGA and retimed by HMC7043/7044 to `ref_clk` and `dac_clk`
- by clock-gen and mesured…
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I am trying to execute a base example on VC707, but it seems I am doing something wrong. The VC707 has 5 gpio buttons and 8 gpio leds.
A VHDL test they run perfectly, but trying to implement the same…
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I am trying to build a base example for VC707 board. My first issue is that I have a differential clock input clk_p clk_n. Which is the cleanest way to integrate with Chips-2.0?
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[x] some addresses of the device do not respond to reads, causing CPU lockup
[x] interrupts do not work