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A mesecon FPGA performs computation on each input change, which takes CPU time. But, it has only 4-bit input, which is just 16 possible states. Thus its output can be precomputed and stored in the met…
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Hello!
First great job on this library! It's very clean and extensive.
I wanted to ask if there's any plans to add direct support for a number of digital components - from various logical gates …
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**Is your feature request related to a problem? Please describe.**
We need to support the legacy data feed that we host at /features.json and /features_v2.json, but we don't want it to constrain or c…
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**Describe the bug**
The Direction of Elements at some places is shown in the properties by` Orientation `while in some places it is displayed `Direction`. Please Refer to the Screenshots.
**To Re…
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![20220604153602_1](https://user-images.githubusercontent.com/51568939/171980650-641ca81e-50a3-4fdc-bdfe-b06181c2030c.jpg)
Two problems, first a graphical glitch with the drag/drop coding window cl…
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Add custom channels for TOR/SVR warning IBW tags. This way a subscription could be made against a certain tag.
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I think that the best way to make sure that every single Verilog file is bug-free is to create a test bench for each one. I did this for the logic gates on my old machine, but unfortunately I don't ha…
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_From [andre.knoerig@gmail.com](https://code.google.com/u/andre.knoerig@gmail.com/) on June 18, 2011 09:08:09_
I think this would be nice, especially for schools.
I'm thinking of basic battery-powere…
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https://youtube.com/playlist?list=PLT0pUL77e5RGf9oXqowMgMzQPfyhaC3qr
Commit Links are on Readme
https://github.com/aaditgupta21/geniuzes#week-7