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**Describe the bug**
STM32WL does not support HSE correctly as RCC clock source. Also STM32WLxx has two div option for HSE, but there is not way to select HSEDiv. I have tested on my STM32WL55CC cust…
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`svd2rust` recently released version `0.18.0` which contains some breaking changes. This is the version downloaded and installed when running `cargo install svd2rust`.
When running `make` for this cr…
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Loose issue to track features I want for my project, may change
Feel free to comment if you want to see features of the HAL not listed here.
* [ ] SUBGHZ https://github.com/newAM/stm32wl-hal/iss…
newAM updated
2 years ago
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**Describe the bug**
Adding the LORA module (CONFIG_LORA=y) in prj.conf crashes I2C.
**To Reproduce**
Add the Lora module to any project that uses I2C (tested on a nucleo_wl55jc) using sensor sht…
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**Describe the bug**
Some STM32 series (g0, l0, l4, l5, wb, wl) require `CONFIG_PM_DEVICE` if `CONFIG_PM=y`. However, one should be able to have system PM enabled (`CONFIG_PM=y`) without the need o…
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By Default the RF-Switch CTL1 to CTL3 lines are NC and will cause a HardFault. On my (custom) board, I only utilize a single Pin for the RF switch.
There could be a little documentation on the 3 Pins…
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I have an stlink-v2 hooked up to a newly designed PCB with an stm32wl55ccu7 but can't seem get OpenOCD working. It connects to the target but as soon as I try to connect with gdb, it segfaults due to …
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Hello,
STM32WL dual core is using M0+ and M4. GIT release v1.0.0 has firmware for both.
but when we compiled the M0+ "LoRaWAN_End_Node_DualCore" source binary size is unexpectedly too large
Bin …
PG430 updated
3 years ago
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https://github.com/ARMmbed/stm32customtargets/blob/e7db2bbc78af3db31695a252e8b9f243bc37d754/TARGET_STM32WL/TARGET_LORA_E5/PeripheralPins.c#L133-L159
I would like to use the LPUART on PC0+PC1. I've …
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**Summary:**
This issue is to discuss possible platforms and environments that we could investigate/develop around the ST node FW.
Actions will be taken based on this discussion and separate is…