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Hello,
I am trying to make compile, but I found some errors from my Linux environment.
```
bpmlab2 ~/xilinx/kiman/PandA/PandABlocks-FPGA $ make
/bin/sh: 1: ./common/python/parse_git_version.py:…
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https://github.com/MEGA65/mega65-core/blob/c1954d254a64a65d1a05083dcd4cb5262f61ca88/src/vhdl/viciv.vhdl#L1689
is current VHDL can be compiled? I have a lot of issues with signal multi-drivers like …
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Hi @tgingold, I know that you are still working with the inference of BRAMs. There are several examples from Xilinx, but only four of them fails with ```ghdl --synth``` (and probably also #1244 when s…
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I successfully built this adapter and it tested out fine in a Commodore B128-80 lo-profile model using Commodores own dealer diagnostics cartridge and loopback connectors. I used OSHPark.com for my …
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Hi all,
Does any one still do the project, I am now designing a single board for this, means all in one board(FPGA+HDMI splitter) , but I think I can't do the software, could someone work together …
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First, thank you for sharing your valuable AXIS and Ethernet repositories.
I'm currently using your 'eth_mac_1g' MAC on a VCU118 platform, and noticed that you don't drive the 'tx_ptp_ts' and 'rx_ptp…
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Made it to step 6 of the NetFPGA-1G-CML wiki tut... Everything has worked as described by the wiki (after trimac.xcf hoopla) up until this - and this one leaves me completely stumped... Any suggesti…
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Another example from Xilinx (ISE): [ram_protected_sharedvar.vhd.zip](https://github.com/ghdl/ghdl/files/4497287/ram_protected_sharedvar.vhd.zip)
It is a Dual Port BRAM (probably, it will fail for t…
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First of all, the previously reported issues are now working :-D
Again, it is an example from Xilinx (an ISE example). It is synthesized with ISE and Vivado ([here the logs](https://github.com/ghdl…
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Firstly, thanks for doing work to improve Yosys compatibility with existing Xilinx code bases. The work is greatly appreciated! I'm very interested in supporting any work which makes Yosys a more viab…