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When using a RAMB36E2, control inputs to the cell map to two physical bel pins (for the upper and lower halves) - see the below screenshot.
![Screenshot from 2019-06-19 17-01-22](https://user-images.…
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Hi,
currently, there is no subfolder for source files. Instead, the first package directory "com" is directly inside the project's root directory. In the gradle build, this first package directory …
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**Issue by [mithro](https://github.com/mithro)**
_Thursday Jun 06, 2019 at 23:26 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/92_
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How do you suggest adding support for us…
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I am trying to create a Module from a checkpoint file and metadata generated for an component that has been implemented out of context. However during I get the following Exception:
Exception in thre…
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I am trying to use rapid_compile_ipi on my block design however I am getting the following error message:
ERROR: Could not find file: /home/dan/blockCache/5e87d6aca5f340f9/board_2x2_simple_output_0…
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I am trying to run rapid_compile_ipi on the simple IPI design described in the Building Basic Elements for IPI tutorial given on the Xilinx website (https://www.xilinx.com/support/documentation/univer…
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A few suggestions to make the RapidWright installation process go more smoothly:
- **mention what is possible with the Quick Start (standalone jar) approach** -- as far as I understand, the Vivado tc…
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The instructions on the docs here -> http://www.rapidwright.io/docs/RapidWright_Jupyter_Setup.html use a lot of screenshots which make it impossibe to copy+paste the output into your notebook.
Coul…
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When I try and use a `Unisim.LUT6_2` I get the following error;
```
java.lang.RuntimeException: java.lang.RuntimeException: ERROR: This unisim LUT6_2 is not supported on ARTIX7
```
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The current `repr` output of a `SiteInst` object looks like the following;
```
inst "null" "null",placed CLBLL_R_X17Y131 SLICE_X26Y131
```
Current confusing parts of this string are;
* The r…