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[Prjxray-db](https://github.com/f4pga/prjxray-db) structure has been changed some time ago. As a result CI fails to build data files for most of architectures available in prjxraydb.
The errors (`F…
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The most recent videos on the pages site are from 2019 -- that's before Linux on LiteX on Arty worked with SymbiFlow.
Maybe there's an update coming along with the f4pga update?
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The tool we are generally using for doing bitstream loading is OpenOCD (which is also what is packaged in conda and referenced by cmake) yet the instructions at https://symbiflow.readthedocs.io/en/lat…
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0 verbose cli [
0 verbose cli '/root/Desktop/project/f4pga-bitstream-viewer/nenv/bin/node',
0 verbose cli '/root/Desktop/project/f4pga-bitstream-viewer/nenv/bin/npm',
0 verbose cli 'run',
0 …
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Consider the following; important is the local function inside the generate statement which then is used right after it is defined
```systemverilog
module C #(
parameter int width = 2,
p…
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Hello @tcal-x
I am using the Digilent Arty board containing the 100T device with the CFU Playground on the default **proj_template** example.
With the following command line, I see the followin…
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https://developers.google.com/speed/pagespeed/insights/?url=symbiflow.github.io
First paint is 2.6 seconds!
- [ ] Properly size images
- [ ] Others?
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Need support for Project X-Ray for my kintex 7 xc7k325t
for implementing a blinky like done here https://github.com/kintex-chatter/xc7k325t-blinky-nextpnr
somhi updated
2 years ago
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As soon as I add bram/dsps from the topmost clock region, the design fails,
complaining that more bram/dsps are instantiated than available on the device.
(Although they clearly exist).
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SYMBIFLOW-CLASSROOM-PROJECT
In SystemVerilog a parameter to a module can be define in one of two ways:
```
module riscv_mem #(parameter TEXT_MEMORY_FILENAME) (clk, rst, PC, , ...);
```
as w…