chipsalliance yosys-f4pga-plugins issues

chipsalliance / yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

https://f4pga.org

Apache License 2.0

83 stars 46 forks source link

issues

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f4pga-plugins conflicts with Yosys (recent versions)

#552 amirarjmand93 opened 2 weeks ago
0
Fix abc9 examples

#551 saaramahmoudi closed 1 month ago
0
Not supported while loop inside "initial" block

#550 iv2nl0b9v opened 5 months ago
0
Not supported while loop

#549 iv2nl0b9v opened 5 months ago
0
Not supported SystemVerilog bit vector functions

#548 iv2nl0b9v opened 5 months ago
1
Not supported blocking and non-blocking assignments to the same array

#547 iv2nl0b9v opened 5 months ago
0
Remove the SystemVerilog plugin

#546 kbieganski closed 9 months ago
0
Bump plugins version

#545 kbieganski closed 9 months ago
0
Upgrade GitHub actions with deprecation warnings

#544 timkpaine opened 9 months ago
2
Rename synth_quicklogic to synth_quicklogic_f4pga to not conflict with yosys builtin

#543 timkpaine opened 9 months ago
2
latest yosys: ast process_format_str() changed, plugin won't compile.

#542 hzeller opened 10 months ago
4
Undef a macro that clashes with a UHDM class.

#541 hzeller closed 10 months ago
2
Remove UHDM coverage report functionality

#540 kbieganski closed 10 months ago
1
Array Parameter Not Accepted

#539 QuantamHD opened 10 months ago
6
Allows Union Types in Parameter Fields

#538 QuantamHD closed 10 months ago
2
design_introspection-plugin missing README.md file

#537 mithro opened 10 months ago
0
Bump plugins version

#536 tgorochowik closed 10 months ago
0
incorrect arithmetic shift

#535 grotival closed 10 months ago
6
Fix memory leaks detected by ASAN.

#534 mglb closed 1 year ago
0
systemverilog-plugin: fix convert_range function

#533 kamilrakoczy closed 8 months ago
1
reversed ranges

#532 wsipak opened 1 year ago
0
systemverilog plugin: changes required for newer Surelog version

#531 kamilrakoczy closed 10 months ago
0
systemverilog-plugin: Fix few ASAN issues

#530 mglb closed 1 year ago
0
yosys-systemverilog: fix multirange with dot usage

#529 kamilrakoczy closed 1 year ago
0
Fix hier path processing

#528 wsipak closed 1 year ago
0
install commands don't respect DESTDIR to install into a stage directory

#527 yurivict opened 1 year ago
1
pmgen.py is downloaded without checking the cryptographic hash

#526 yurivict opened 1 year ago
0
revert setting current_struct_elem in expand_dot

#525 wsipak closed 1 year ago
0
indices are mixed up when assigning values in array of array of packed struct

#524 grotival closed 10 months ago
8
systemverilog-plugin: fix anonymous enum when declared in submodules

#523 kamilrakoczy closed 1 year ago
1
antmicro/yosys-systemverilog#1743: Compensate for chipsalliance/Surelog#3670

#522 hs-apotell opened 1 year ago
10
duplicated ranges

#521 wsipak closed 10 months ago
0
systemverilog-plugin: allow multirange access in dot access

#520 wsipak closed 1 year ago
0
systemverilog-plugin: fix parsing unsized unbased consts

#519 kamilrakoczy closed 1 year ago
1
systemverilog-plugin: split line and column in uhdmast_assert_log

#518 kamilrakoczy closed 1 year ago
0
Handling of "'1" expression

#516 grotival closed 1 year ago
3
Tcl-tests: expand environment variables.

#515 hzeller closed 1 year ago
0
systemverilog-plugin: Remove temporary test files.

#514 mglb closed 1 year ago
0
systemverilog-plugin: fix unnamed packed array

#513 kamilrakoczy closed 1 year ago
1
systemverilog-plugin: update remove module message

#512 kamilrakoczy closed 1 year ago
0
Process vpiArrayTypespec the same way as vpiPackedArrayTypespec

#511 wsipak closed 1 year ago
1
do not get value size of a constant from its typespec

#510 wsipak closed 1 year ago
0
systemverilog-plugin: add support for multiple variables declared in anonymous enum var

#509 kamilrakoczy closed 1 year ago
1
systemverilog-plugin: Enable non-synthesizable code removal in Surelog.

#508 mglb closed 1 year ago
2
systemverilog-plugin: fix packed arrays of enums

#507 kamilrakoczy closed 1 year ago
2
sv-plugin: Strip the node name using parent name instead of "."

#506 mandrys closed 1 year ago
4
Check for typedefs before calculating width

#505 wsipak opened 1 year ago
0
systemverilog-plugin: adapt visit_object calls to new UHDM api

#504 kamilrakoczy closed 1 year ago
0
ERROR: member top_flag_t of a packed union has 3 bits, expecting 24

#503 QuantamHD closed 1 year ago
8
sv_plugin: unhandled typespec in process_typespec_member:

#502 QuantamHD closed 1 year ago
5