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First of all thanks for this awesome project!
So I tried to follow the instructions to run the `build-and-run-sprites-demo.sh` inside `simulator/`.
After compiling the riscv cross-toolchain dire…
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I am compiling my own bootloader for a PicoRV32 soft CPU with the `-nodefaultlibs` flag. When I enable LTO, the linker throws ```undefined reference to `memset'``` while there is no _memset()_ call.
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I'm trying to build toolchain on ubuntu 20.04 for Windows using mingw-w64:
```
./configure --prefix=/opt/riscvgcc --enable-multilib --with-host=i686-w64-mingw32 --without-system-zlib
make -j
```…
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Dear developers, I followed the quickstart guide document to setup my environments(installed latest git versions via git-clone-make or AUR xxx-git package), and in a fresh repository clone I got these…
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```
3.1.4 嵌入式应用处理器——ORCA
**PicoRV32**是由VectorBlox公司设计的一款32位标量处理器，目标是应用于嵌入式领域，采用VHDL编写，实现了RV32IM，也可以移除其中的M扩展，也就是移除乘法除法扩展，从而减少芯片占用资源，甚至可以移除与定时器有关的指令，从而仅仅实现RV32E。当将ORCA作为一个软核下载到FPGA上的时候，其资源占用与主频如表5所示…
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The example start.S switches to a dedicated stack for the interrupt handler. Is this strictly necessary? I mean can I just leave the stack pointer alone so that whatever the current stack is used fo…
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Dear all,
Please apologize for the very basic question but I cannot find any behavioral or rtl description of the picorv32_core (wthether in Verilog, C scala...).
I am sure I missed something very…
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A bit a niche circumstance I admit, but I sometimes do some work ona windows desktop via a Cygwin environment with verilator and GTKWave installed as described here: https://zipcpu.com/blog/2017/07/28…
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Version: 0da4562b518d88ff95e086ea1350b4e96156aa99
This error was found synthesizing a picorv32 chip.
I've attached an archive with a script to reporduce the error
[openroad_infite_loop.tar.gz](…
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I get a trap on a divu instruction on a Cyclone V with Quartus 15 or 20 when building with ENABLE_DIV and ENABLE_FAST_MUL or ENABLE_MUL. It works in both verilator and iverilog, just not on the target…