SymbioticEDA riscv-formal issues

SymbioticEDA / riscv-formal

RISC-V Formal Verification Framework

ISC License

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issues

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RV32I and RV64I

#61 quantrpeter opened 8 months ago
0
syntax error in quickstart

#60 gipsyh opened 2 years ago
1
Is this repo no longer active?

#59 jiegec opened 2 years ago
0
typo

#58 mesaperry opened 2 years ago
0
Some confusion about skip option

#57 LIIT0215 opened 2 years ago
0
are rvfi_valid and rvfi_trap mutually exclusive.

#56 eroom1966 opened 2 years ago
0
Can WARL read-only be handled in csrw_check?

#55 silabs-robin opened 3 years ago
0
make explicit the reg_check constant values

#54 silabs-robin opened 3 years ago
1
rvfi_reg_check is possibly broken (picorv32 also fails the assertion)

#53 silabs-robin opened 3 years ago
3
When is rvfi_halt supposed to be used?

#52 Silabs-ArjanB closed 3 years ago
0
Support for Zce?

#51 Silabs-ArjanB closed 3 years ago
0
How to set values in the genchecks.cfg file?

#50 ShashankVM closed 3 years ago
0
Instruction checks: non-universal assertions should be generated based on instruction type

#49 silabs-mateilga opened 3 years ago
0
"ERROR: syntax error, unexpected TOK_RAND" in quick start guide

#48 regymm closed 3 years ago
2
typo

#47 wasserfuhr opened 3 years ago
0
Make basedir overridable, add incdir optional harg

#46 slan opened 3 years ago
1
Fix some syntax errors

#45 leonschoorl opened 3 years ago
0
Debug modelling

#44 silabs-PaulZ opened 3 years ago
0
Fix PREUNSAT errors in QuickStart Guide Exercise 1 (picorv32)

#43 DonaldKellett closed 2 years ago
1
Incorrect width of insn_funct6 in I-type (shift variation) instruction format?

#42 DonaldKellett opened 4 years ago
0
OOPS forget i said anything

#41 ewoudje closed 4 years ago
0
Value of rs1 during CSR*I instructions

#40 olofk opened 4 years ago
2
JAL handling procedure

#39 RojasMilo opened 4 years ago
1
Misaligned JAL(R) RD register writeback expectations

#38 ultraembedded closed 4 years ago
4
Add support for optionally ignoring rmask

#37 chgentso closed 4 years ago
1
Failed Checks in picorv32 Verification Following Quickstart Guide

#36 myrealname opened 4 years ago
3
more references

#35 llelf closed 4 years ago
0
Adding support for a newRISC-V processor to riscv-formal

#34 weedmank opened 4 years ago
4
Proposal: RISC-V formal verification project

#33 mrLSD closed 4 years ago
1
RVFI load/store error detection

#32 udinator opened 4 years ago
3
Small fixes for monitor generation

#31 jleahy closed 4 years ago
0
RVFIMON generate.py not creating ialign16

#30 jasonB221 opened 4 years ago
1
Unexpected result in insn_div when dividing by 0 when not using RISCV_FORMAL_ALTOPS

#29 Zeldax64 closed 5 years ago
2
Add a "mode" option to cfg file

#28 AlAlves closed 5 years ago
1
Note for ignoring rvfi_intr

#27 towoe opened 5 years ago
0
Don't use rd_wdata of instructions that trapped in the reg check

#26 mtvec closed 5 years ago
2
Register checks do not seem to be checking anything

#25 mtvec closed 5 years ago
3
Clarification needed for verification of MUL/DIV

#24 mtvec closed 5 years ago
3
Update checks.cfg

#23 AlAlves closed 5 years ago
0
Cannot generate trap on bad jump address (c.j/c.jal)

#22 aignacio closed 5 years ago
3
Update cores/serv/checks.cfg

#21 AlAlves closed 5 years ago
0
Initial questions about getting started with a new core

#20 aignacio closed 5 years ago
2
C Extension Decoding

#19 ben-marshall closed 5 years ago
3
Notion of a memory bus error

#18 ben-marshall closed 5 years ago
1
rocket verification

#17 towoe closed 5 years ago
1
Fix monitor/generate.py to support macros besides RISCV_FORMAL_COMPRE…

#16 yx9527 closed 5 years ago
0
Endianness Confusion Load Inst test

#15 mdxg closed 5 years ago
2
Serv

#14 cliffordwolf closed 5 years ago
0
no vcd trace

#13 towoe closed 5 years ago
6
Monitor generate has no misa check

#12 towoe closed 5 years ago
1