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In section 6.10.6 of the specification, the state messages contain an optional attribute called `informations`. This, in turn, includes other attributes, one of them is `infoReferences` which is of th…
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I noticed the latest docs show that a simple `@always_comb` block can be converted to a Verilog `assign` statement with a `wire` type for the output: http://docs.myhdl.org/en/latest/manual/conversion_…
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I was trying to make some fancier landing gear using this logic sequence:
- landing gear ON > rail ON > timer > rotor ON
However, when the landing gear are switched off, the OFF signal proceeds in…
Nas0m updated
4 years ago
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The plonky2 crate is not documented properly.
Even though the whole thing is open source, anyone who wants to use it must figure out what most of the API does by code digging.
Notable examples inc…
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hello, is possible to implement ARM cpu in logicemu?
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The current implementation of memory for simulation is unrealistic in that it provides "immediate" access to data; as soon as the address is applied to the input, the content word can be read from the…
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### Description
I'd like to be able to connect multiple sequencers to a single block, or multiple outputs to a piston for example.
With those possibilities you can do wayyy more with the given b…
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I recently want to run Circuit ORAM on EMP-AGMPC (ah, both come mostly from you), so the main challenge is to write `prepare_deepest` and so on.
In Obliv-C, writing `prepare_deepest` would be simpl…
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### Feature description
Being able to toggle whether the Shock Detector sends a signal when impacting something. Preferably by sending a red/blue signal to the Shock Detector.
### Feature purpose
W…
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Hello,
I was watching the showcase _Automatic Gate Schedule Configuration_ at showcases/tsn/gatescheduling/sat/omnetpp.ini .
But when I set all kinds of traffic to one single priority so t…