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The current SRAM design exposes the sense amplifier directly on the output. This means that during precharge the output of DOUT is in undetermined digital state. This is reflected in the verilog code …
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The read_liberty command reads a cell library, but it does not recognize memories. These require support for the memory cell type. You can see an example from OpenRAM at:
https://github.com/VLSIDA/…
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I will just describe an example. The code for RISC-V CPU with the compressed instruction extension is a mix of 32 and 16 bit instructions, this meas 32bit instructions are not always 32bit aligned.
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jeras updated
5 years ago
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Hello mguthaus.
I am at the beginning of most entry.
but when i responded Readme, Unit test clogged up in this part.
For info, 00_code_format_check_test.py is pass, I installed freepdk45 t…
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Hello mguthaus,
While am running 04_pinv_test.py for tsmc technology, i am getting an error like
"ERROR: runTest (__main__.pinv_test)
-----------------------------------------------------------…
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Hello Matt,
I am facing an issue, while i am writing a gds file then gds2writer.py is showing an error like
" writer.writeToFile("sqrin.gds")
File "/home/anagar/work/cwork/pycells/gdsmillPkg/g…