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VLSIDA
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OpenRAM
An open-source static random access memory (SRAM) compiler.
http://www.openram.org
BSD 3-Clause "New" or "Revised" License
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Runtime
#245
mbautista-lab
opened
1 week ago
8
Not generate certain module
#244
YWJ226
closed
3 weeks ago
1
Possible minor error on the documentation related with the ROM usage
#243
PabloUlises
opened
1 month ago
0
Power estimation seems too high
#242
Lukemagik
opened
1 month ago
14
Support for ASAP7 PDK
#241
mbautista-lab
closed
2 months ago
1
Errors hidden on default loglevel, but visible on verbose loglevels.
#240
c-93
opened
2 months ago
0
Question: What is the correct allignment in SKY130? Intermediate Pins are not connected to the grid. Likely user mistake.
#239
c-93
opened
2 months ago
10
Import custom file
#238
YWJ226
closed
2 months ago
3
No liberty file is created for ROMs
#237
galv
closed
2 months ago
2
Routing error due to high (vertical) density?
#236
c-93
opened
2 months ago
1
Importing a custom GDS file.
#235
YWJ226
closed
2 months ago
7
Stimuli Generation - sram_func.py or gen_stimuli.py
#234
abdullahsahruri
opened
2 months ago
0
multiports bitcell
#233
YWJ226
closed
2 months ago
1
ROM >= 8k fails to build
#232
urish
opened
3 months ago
3
ROM dump + replace contents
#231
urish
opened
3 months ago
0
Ensure rom_data dir exists
#230
urish
opened
3 months ago
3
Support for PROBE PDK
#229
glzhou97
opened
3 months ago
4
Error in SRAM creation with banks
#228
KanishR1
opened
4 months ago
6
openram.py doesn't exist in any tree
#227
msarwarx1
opened
4 months ago
1
Unable to read configuration file
#226
cannotgetaname
closed
5 months ago
3
Add ROM config for gf180mcu
#225
mole99
closed
3 months ago
5
Feature request: PROM
#224
spth
closed
5 months ago
1
Fix wire capacitance unit in sky130, gf180
#223
ubfx
opened
5 months ago
0
Support for ASAP7 (open source 7nm PDK)
#222
StephenMoreOSU
closed
5 months ago
1
How to generate an SRAM with more than two ports?
#221
HotCoCoC
closed
5 months ago
5
LVS mismatch for some sky130 example SRAMs
#220
ubfx
opened
6 months ago
0
Use volare in Makefile
#219
mole99
closed
5 months ago
11
Use Volare as PDK version manager
#218
mole99
closed
5 months ago
5
LVS mismatch errors in SKY130 SRAM
#217
KEVIN09876
opened
6 months ago
1
ROM signal names do not match model
#216
mole99
closed
6 months ago
2
Add LEF output for ROM
#215
mole99
closed
6 months ago
0
Virtuoso Layout using freepdk45
#214
tomaschoi03
closed
7 months ago
2
Generating bit cell array with custom bit cell.
#213
tomaschoi03
closed
7 months ago
4
scn3me_subm tech CellProperties error
#212
htm23x
closed
8 months ago
4
Pin iterator not found error in hierarchy_layout.py
#211
htm23x
closed
8 months ago
11
Validate tech_name param in compiler/globals.py
#210
htm23x
opened
8 months ago
2
4 test case failed for freepdk and scn4m
#209
z4fang
closed
6 months ago
4
Support for IHP PDK
#208
htm23x
opened
8 months ago
1
sram_compiler.py - python 3.8.18 posixpath error
#207
htm23x
closed
8 months ago
4
Errors on characterization process
#206
andreili
opened
8 months ago
0
Guideline needed for the insertion of a foreign pdk like gpdk45 into OpenRAM flow
#205
faisaladilquadery
closed
9 months ago
1
Missing pins issue for single port memory using sky130
#204
NamrathaCTR
closed
8 months ago
5
Invalid column decoder encountered when generating large-scale SRAM
#203
Chuld
closed
11 months ago
3
installaion problem and configuratiom problem
#202
haotommy
closed
11 months ago
13
Anaconda install problem
#201
haotommy
closed
11 months ago
8
having issue while trying to create sram for sky130 pdk
#200
bharath19-gs
closed
10 months ago
5
data not getting written into memory cells
#199
KolliparaAbhishekAnand
opened
11 months ago
6
How to use the .sp&.v generated after executing config on other tools
#198
haotommy
closed
1 year ago
12
the meaning of local_array_size
#197
hanm2019
closed
1 year ago
3
Adding linear regression model breaks flow
#196
jackpanderson
opened
1 year ago
1
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