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Hi my name is John and I am also a PhD student looking to write a new HDL borrowing ideas from Rust and Clash and I was wondering about the nature of your project.
So if I am understanding it right…
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I am trying to produce a grammar to parse the SystemVerilog HDL, however I'm experiencing some inconsistent behaviour when parsing numbers.
In SystemVerilog, by default numbers are interpreted as de…
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Guys, I am trying to run my cocotb testbench with Icarus. I have like 6 verilog modules - all included in one top level module. I have prepared my test and the make file which when I try to execute, I…
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I'm experimenting with a generator that produces HDL packages containing constants defined in a core file. The current version uses Jinja templates. There are a total of three files at the moment: the…
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Hello everyone,
I know there is enough work on the todo lists, but I was wondering if GHDL should eventually offer a [Language-Server-Protocol](https://github.com/Microsoft/language-server-protocol…
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I'll try to be some more verbose and then fire off the PR .
once I find the correct linguistic fokus.
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Updated config style inspired by the method used in the DE0_Nano_SoC_DB25 project
Created a …
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In order to keep compatibility with tools partially supporting _SystemVerilog_, especially at the top level, it may be a desired, that _rggen_ generates, on request, a top-level pure VHDL/Verilog wrap…
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Some linters have not only **ERROR**/**WARNING** severity levels, but also **NOTE** message types. So, it might make sense to add a third **NOTE** severity support level, so that it can be scoped and …
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Hello,
I am one of the contributors to [Verilog HDL support for VS Code](https://github.com/mshr-h/vscode-verilog-hdl-support). I request you to join with us to make Verilog/SystemVerilog support i…