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Hi everyone,
I'm a master graduating student at Scuola Superiore Sant'Anna in Pisa.
For my thesis, I'm trying to accelerate a custom network model on a ZCU102 ultrascale+ using the new Vitis-AI to…
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Hi.
I'm trying to using Alveo U50 by Vitis AI.
My neural network model is divided four dpu-subgraph and the others are for cpu runner.
I created runner object for cpu using VART API like below:…
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Hi everyone,
I'm a master graduating student at Scuola Superiore Sant'Anna in Pisa.
For my thesis, I'm trying to accelerate a custom network model on a ZCU102 ultrascale+ using the new Vitis-AI tool…
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Hello, how are you?
In https://github.com/Xilinx/xup_vitis_network_example/issues/11#issuecomment-768897746, you mentioned that the function of ol.networklayer_0.arpDiscovery() is achieved by pinging…
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I am using Vitis HLS 2019.2 to export RTL (generating a .xo file) from this network (https://github.com/fastmachinelearning/hls4ml-tutorial/blob/master/part1_getting_started.ipynb).
When I try it,…
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Hi. Me again. I meet some problems about the design of the project.
I have several clients sending packages to the only one FPGA, and the FPGA is considered to answer each client correctly. However…
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In your Readme.md, xilinx-u250-gen3x16-xdma-3.1-202020-1 is not supported by Vitis 2020.1. So I changed to the Xilinx_u250_xdma_201830_2 platform.
But I meet the following problem when using the Xi…
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Sorry to bother again but I'm confused about the definition of destination ID. ( https://github.com/Xilinx/xup_vitis_network_example/blob/4955fa3c957b96254405255499a155d47b50bc82/Basic_kernels/src/krn…
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I find that in vnx-benchmark-rtt.ipynb, you use traffic_generator_1_0 for 'LOOPBACK' and traffic_generator_1_2 for 'LATENCY'. But in vnx-benchmark-throughput.ipynb, you use traffic_generator_1_1 for '…
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Hi,
I have downloaded the cf_resnet50_imagenet_224_224_7.7G_1.3 and have tried to compile it.
There was an error occurred during compilation.
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