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xup_vitis_network_example
VNx: Vitis Network Examples
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Fix typo in Alveo U50 Vivado Part Number
#129
C1bergh0st
closed
2 months ago
5
Test Link with and without RS-FEC
#128
mariodruiz
closed
5 months ago
0
RS-FEC test
#127
mariodruiz
closed
5 months ago
0
Test link with RS-FEC
#126
mariodruiz
closed
5 months ago
0
Initial test link code
#125
mariodruiz
closed
5 months ago
0
Compiling issue during routing phase with U250
#124
GiacomoLevrini
closed
5 months ago
4
Can the XUP vitis network design work with 10G/25G Ethernet IP instead of the existing 100GEthernet IP ?
#123
lizajoseph
closed
5 months ago
3
Alveo u50 card to NIC card physical link is not getting detected
#122
lizajoseph
closed
7 months ago
8
Compiler error with Alveo xilinx_u50_gen3x16_xdma_5_202210_1 with Vivado and Vitis Version 2023.1 and XRT xrt_202310.2.15.225_20.04-amd64-xrt
#121
lizajoseph
closed
7 months ago
6
Can a 10G or 25G NIC card be used to execute and implement this design with Alveo u50 card?
#120
lizajoseph
closed
8 months ago
4
Implement 100G TCP/IP Offload Engine on U250
#119
HirunaVishwamith
closed
8 months ago
1
Replace deprecated numpy aliases of builtin types with the actual types
#118
green4free
closed
10 months ago
1
Configurable hw socket table size
#117
quetric
closed
9 months ago
8
How to set UDP MTU size and the UDP size in VNx?
#116
liubenyuan
opened
1 year ago
0
Need ping before UDP transactions
#115
liubenyuan
closed
1 year ago
1
Nolink when porting to ADM-PCIE-9V3
#114
liubenyuan
closed
1 year ago
3
Fix of unresponded ICMP under Vitis 2022.2
#113
HongshiTan
closed
1 year ago
0
Fix of unresponded ICMP under Vitis 2022.2
#112
HongshiTan
closed
1 year ago
0
Add support for U55N
#111
HongshiTan
closed
1 year ago
1
fix bugs in the vnc-basic-image-transfer.ipynb
#110
zhangchenqi123
closed
1 year ago
0
In branch `host_xrt`, the tx end can send the packets but the rx end keeps waiting.
#109
zhangchenqi123
closed
1 year ago
1
Bug reported: name `ol` is not defined.
#108
zhangchenqi123
closed
1 year ago
7
Exception: 'RuntimeError("There is no current event loop in thread \'Dask-Default-Threads-67128-0\'.")'
#107
zhangchenqi123
closed
1 year ago
2
About xilinx_u280_xdma_201920_3
#106
pengjintao
closed
1 year ago
1
HW emulation support with SystemC model
#105
quetric
opened
1 year ago
0
Build problem for U50
#104
danwetzel
closed
2 months ago
8
How to send packets to multiple destinations in basic design
#103
pouya-haghi
closed
1 year ago
3
How to see the GUI of cmac_kernel in VIVADO ?
#102
zhuofanzhang
closed
1 year ago
2
Reducing CMAC/NetworkLayer Frequency
#101
ChunshuWu
closed
1 year ago
2
CMAC: multi-mode padding and RSFEC sub-mode 1
#100
quetric
closed
1 year ago
10
Added frame padding to CMAC kernel
#99
quetric
closed
1 year ago
1
CMAC long bring-up time after xbutil reset
#98
TheFlux7
closed
1 year ago
2
Fixes for new pynq version
#97
TristanLaan
closed
1 year ago
0
Add RS-FEC support to CMAC layer
#96
TristanLaan
closed
1 year ago
1
Implement statistics function CMAC and missing loopback functions
#95
TristanLaan
closed
1 year ago
0
Ping not working in "basic" design
#94
pouya-haghi
closed
1 year ago
7
Running vnx-basic notebook with an FPGA and a 100Gb NIC in different hosts
#93
pouya-haghi
closed
1 year ago
9
Where is the definition of the "_start()" in the DataMover class?
#92
Ossic
closed
1 year ago
3
How to test the PCIe bandwidth in the benchmark design?
#91
IskandarZhang
closed
1 year ago
1
Alveo U50 stat_rx_status always 192
#90
victornvq2
opened
2 years ago
7
Alveo U25 compatibility
#89
erenkal
closed
2 years ago
1
Connecting U250 with Ethernet NIC using QSP fiber cable.
#88
karthickpython
closed
1 year ago
2
Payload size limitation [XRT]
#87
KoalaYuFeng
closed
2 years ago
8
Failed generating target for U50 while creating FPGA bitstream
#86
yangxiaomaomao
closed
2 months ago
7
Is it possible to connect one QSFP port to second QSFP port of same board (alveo U250) instead of 2 alveo cards?
#85
Sarika124
closed
5 months ago
12
Failed to generate bitstream after passing synthesis and implementation [Vivado 2021.1, Alveo U250]
#84
charles-typ
closed
2 years ago
2
Failed generating target for U50 while creating FPGA bitstream
#83
fujimotokua
closed
2 months ago
3
[XRT] XRT related network performance (mm2s_buf.sync_to_device)
#82
anonymous1782
closed
2 years ago
1
Query: (1) why throughput higher than theoretical, (2) why lower throughput with 128B payload.
#81
108anup
opened
2 years ago
13
Does this repository support QDMA?
#80
byeongkeonLee
closed
2 years ago
4
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