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### Version
Yosys 0.45+139 (git sha1 8e1e2b9a3, x86_64-apple-darwin21.4-clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
### On which OS did this happen?
macOS
### Reproduction Steps
Extract [tmpfile-bug.zip…
agrif updated
1 month ago
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If either a gate level design or tech mapped design (eg adder cell mapping) has multi-output gates, rmp fails:
```
Warning: Detected 1 multi-output gates (for example, "FAx1_ASAP7_75t_R").
** cmd…
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Hi,
I was trying to make the tool work for some time. But it seems like there is something I am missing.
I made a simple robot FSM
[robot.txt](https://github.com/reactive-systems/MCHyper/files/65…
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## Description
This issue is not so much an issue, but a compilation of my findings when researching how to use abc to verify hardware models using PDR. More specifically, what commands to run to b…
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### Version
Yosys 0.40+25 (git sha1 171577f90, sccache x86_64-w64-mingw32-g++ 13.2.0 -Os)
### On which OS did this happen?
Windows
### Reproduction Steps
1. Save this file as `bad.rtlil`:
``…
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I've done some tests with liveness proofs using PSL properties like:
```vhdl
assert always (rose(a) -> eventually! b);
```
I noticed that such constructs are processed by GHDL (and Yosys), but…
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Consider the following C function:
```
#include
uint32_t mult(uint32_t x) {
return x * 0x85EBCA77U;
}
```
We can compile the code to LLVM like so:
```
$ clang -emit-llvm -c mult.c -o…
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The installation instructions should be updated, or maybe super_prove should be changed to an optional dependency for running tests.
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When outputting the graph to networkx using `to_nx`, the output labels are incorrect. They seem to all be using the label of the first output variant. The example below can be reproduced using the cod…
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1. When reading a file in AIGER format with `&read` and creating the XAG with `&st -m -L 1` then the command `&cec` will return `not equivalent`. But when strashing it again with `&st` the equivalence…